Unit4 - Subjective Questions

Difference between Combinational and Sequential Circuits:

Half Adder:

A Half Adder is a combinational circuit that performs the addition of two single bits. It has two inputs () and two outputs: Sum () and Carry ().

Boolean Expressions:

• Sum (S):
• Carry (C):

Truth Table:

Logic Circuit:
It is implemented using one XOR gate (for Sum) and one AND gate (for Carry).

Full Adder:

A Full Adder performs the addition of three bits (two significant bits and a previous carry input ). It produces a Sum () and a Carry Out ().

Truth Table:

K-Map Simplification:

1. For Sum (S): The minterms are 1, 2, 4, 7. This results in the XOR relationship of three variables.
   
2. For Carry (): The minterms are 3, 5, 6, 7.
   Grouping these on a K-map yields:
   

Full Adder using Two Half Adders:

A Full Adder can be constructed by cascading two Half Adders.

Step-by-Step Logic:

1. First Half Adder:
   • Inputs:
   • Outputs: ,
2. Second Half Adder:
   • Inputs: (from first HA) and
   • Outputs: Final Sum
   • Internal Carry:
3. Final Carry Generation:
   • The final carry is the logical OR of the carry outputs from both half adders.

Circuit Structure:

• Two XOR gates, Two AND gates, One OR gate.

Half Subtractor:

A Half Subtractor takes two 1-bit inputs (Minuend) and (Subtrahend) and produces Difference () and Borrow ().

Truth Table:

Boolean Expressions:

• Difference (D): High when inputs are different.
  
• Borrow (): High only when and .
  

Circuit: Comprises 1 XOR gate and 1 AND gate with a NOT gate (inverter) on input A.

Full Subtractor:

A circuit that subtracts two bits () considering a borrow from a lower significant stage ().

Truth Table Summary:
Inputs: A, B, C. Outputs: Diff (), Borrow ().
Example row: If A=0, B=0, C=1 Diff=1, Borrow=1.

K-Map Analysis:

1. Difference (): Minterms are 1, 2, 4, 7.
   

2. Borrow (): Minterms are 1, 2, 3, 7.
   Grouping on K-Map:

   • Group 1 ():
   • Group 2 ( - wrapped or neighbors): Actually mapped as
   • Group 3 ():

   Expression:

Multiplexer (MUX):
A combinational circuit that selects one of many input lines and directs it to a single output line based on selection lines. It is also called a Data Selector.

4:1 MUX:

• Inputs: 4 Data inputs ().
• Selection Lines: 2 Select lines ().
• Output: 1 Output ().

Truth Table:

Boolean Expression:

Logic Diagram: Constructed using four 3-input AND gates, two NOT gates (for select lines), and one 4-input OR gate.

Implementation using 8:1 MUX:

1. Identification:

   • Variables act as the select lines .
   • The function outputs High (1) for minterms 0, 2, 4, 6.
   • The function outputs Low (0) for minterms 1, 3, 5, 7.

2. Connections:

   • , , .
   • Connect inputs to Logic High (/1).
   • Connect inputs to Logic Low (Ground/0).

3. Result:
   The MUX will now output the value of F based on the binary combination of A, B, and C.

Implementation of 3-variable function using 4:1 MUX:

To use a 4:1 MUX (2 select lines) for 3 variables, we use and as Select lines () and as the data input variable.

Implementation Table:

Connections:

• connected to
• connected to
• connected to
• connected to

De-multiplexer (DEMUX):
A circuit that performs the reverse operation of a multiplexer. It takes a single input data line and routes it to one of output lines based on selection lines.

1:4 DEMUX:

• Input: 1 Data input ().
• Select: 2 Select lines ().
• Outputs: 4 Outputs ().

Logic Expressions:

Operation:
If , the data appears at , while other outputs remain 0.

Decoder:
A combinational circuit that converts binary information from input lines to a maximum of unique output lines. For a given input combination, only one output line is active (High).

3:8 Decoder Design:

• Inputs: (where A is MSB).
• Outputs: to .

Logic Equations (Minterms):

• ... up to ...

Circuit:
Uses three NOT gates (to generate complements of inputs) and eight 3-input AND gates. Each AND gate corresponds to one minterm of the inputs.

Full Adder using Decoder:

A Full Adder has inputs and outputs Sum () and Carry ().

1. Decoder Configuration:

   • Use a 3:8 Decoder. Connect to the select inputs of the decoder.
   • The decoder outputs $0$ to $7$ represent the minterms ( to ).

2. Implementation of Sum:

   • Connect decoder outputs 1, 2, 4, and 7 to a 4-input OR gate. The output is Sum.

3. Implementation of Carry:

   • Connect decoder outputs 3, 5, 6, and 7 to another 4-input OR gate. The output is Carry.

Encoder:
An encoder performs the inverse operation of a decoder. It has (or fewer) input lines and output lines. It converts an active input signal into a coded binary output.

Octal-to-Binary (8:3) Encoder:

• Inputs: (Octal digits).
• Outputs: (Binary representation).

Assumptions:
Only one input is High at a time.

Logic Equations:

• Z (LSB): High if input is 1, 3, 5, or 7.
• Y: High if input is 2, 3, 6, or 7.
• X (MSB): High if input is 4, 5, 6, or 7.

Circuit: Implemented using three 4-input OR gates.

Comparison: MUX vs DEMUX

Comparison: Decoder vs Encoder

1-bit Magnitude Comparator:

Compares two 1-bit numbers and . Outputs: , , .

Truth Table:

Logic Expressions:

1. A = B: High when inputs are same. (XNOR)
2. A > B: High when A=1, B=0.
3. A < B: High when A=0, B=1.

2-bit Magnitude Comparator:

Compares two 2-bit numbers and .

Logic Derivation:

1. Equal ():
   Both bit positions must be equal.
   Let and .
   

2. Greater Than ():
   is greater if MSB , OR if MSBs are equal () AND LSB .
   

3. Less Than ():
   is less if MSB , OR if MSBs are equal () AND LSB .
   

Priority Encoder:
A standard encoder produces an error if more than one input is High simultaneously. A Priority Encoder assigns priority to inputs; if multiple inputs are active, the output corresponds to the input with the highest priority.

4-Input Priority Encoder (D0 to D3):
Assuming D3 has highest priority.

Truth Table:

• X indicates "Don't Care".
• If is 1, output is 11 regardless of other inputs.

Ripple Carry Adder Issue:
In a standard parallel adder (Ripple Carry), the carry out of one stage must propagate to the next. For bits, the delay is . This creates a propagation delay bottleneck.

Carry Look Ahead (CLA) Adder:

• Principle: It calculates the carry for a specific stage based directly on the input signals () and the initial carry (), without waiting for the carry to ripple through previous stages.
• Logic: It uses two functions:
  1. Generate (): A carry is generated independently.
  2. Propagate (): An incoming carry is propagated.
• Speed: Since logic gates generate carries simultaneously for all bits, the delay is constant and significantly lower than the ripple carry adder.

Implementation:

Variable mapping: to Select Lines . to Data Inputs.

Analysis Table:

• If (Row 0): Minterms 0, 1. Function has 0 and 1. Value is $1$ (High).
  
• If (Row 1): Minterms 2, 3. Function has 3. Value matches .
  
• If (Row 2): Minterms 4, 5. Function has neither. Value is $0$ (Low).
  
• If (Row 3): Minterms 6, 7. Function has 6. Value is High when (minterm 6). Value matches .
  

Result:
Connect to Vcc, to , to GND, to NOT().