1What is the fundamental difference between a combinational circuit and a sequential circuit?
A.Combinational circuits have memory, while sequential circuits do not.
B.Sequential circuits contain memory elements and feedback paths, making outputs dependent on present inputs and past states.
C.Combinational circuits are faster because they use a clock signal.
D.Sequential circuits depend only on present inputs, while combinational circuits depend on past outputs.
Correct Answer: Sequential circuits contain memory elements and feedback paths, making outputs dependent on present inputs and past states.
Explanation:
Sequential logic circuits differ from combinational logic circuits because they contain memory elements (like flip-flops) that store the past state. The output depends on both the current inputs and the previous state.
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2Which of the following is the basic building block of a sequential circuit?
A.Decoder
B.Latch or Flip-Flop
C.Full Adder
D.Multiplexer
Correct Answer: Latch or Flip-Flop
Explanation:
Latches and Flip-Flops are bistable multivibrators used as memory elements, which are the fundamental building blocks of sequential circuits.
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3In an SR Latch built using NOR gates, what is the state of the output when and ?
A.Invalid (Indeterminate)
B.Reset ()
C.No Change
D.Set ()
Correct Answer: Invalid (Indeterminate)
Explanation:
In a NOR-based SR latch, if both inputs and are high (1), both outputs and are forced to 0, violating the complementary rule. When the inputs return to 0, the state becomes unpredictable. Thus, it is an invalid or forbidden state.
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4The 'Race-Around Condition' generally occurs in which type of flip-flop?
A.SR Flip-Flop
B.Master-Slave D Flip-Flop
C.D Flip-Flop
D.Level-triggered JK Flip-Flop
Correct Answer: Level-triggered JK Flip-Flop
Explanation:
The race-around condition occurs in a level-triggered JK flip-flop when , , and the clock pulse width is wider than the propagation delay of the flip-flop. The output toggles multiple times within a single clock pulse.
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5What is the characteristic equation of an SR Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:
The next state of an SR flip-flop becomes 1 if Set is high () or if the previous state was high () and Reset is not active (). This gives .
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6Which flip-flop is known as the 'Delay' flip-flop?
A.T Flip-Flop
B.D Flip-Flop
C.SR Flip-Flop
D.JK Flip-Flop
Correct Answer: D Flip-Flop
Explanation:
The D (Data) flip-flop ensures that the output follows the input after a clock transition. Since it transfers data from input to output with a delay of one clock pulse, it is called a Delay flip-flop.
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7In a JK Flip-Flop, if and , the output will:
A.Toggle (Complement the previous state)
B.Remain unchanged
C.Reset to 0
D.Set to 1
Correct Answer: Toggle (Complement the previous state)
Explanation:
The JK flip-flop resolves the invalid state of the SR flip-flop. When both inputs and are 1, the flip-flop enters the 'Toggle' mode, where .
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8What distinguishes a Flip-Flop from a Latch?
A.Latches are edge-triggered; Flip-Flops are level-triggered.
B.Latches are level-triggered; Flip-Flops are edge-triggered.
C.Latches have a clock; Flip-Flops do not.
D.There is no difference.
Correct Answer: Latches are level-triggered; Flip-Flops are edge-triggered.
Explanation:
A latch is transparent (output changes immediately with input) when the enable signal is active (level-triggered). A flip-flop only changes state on the transition (edge) of the clock signal (edge-triggered).
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9What is the characteristic equation for a JK Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:
The characteristic equation of a JK flip-flop is derived from its truth table. It accounts for the Set, Reset, No Change, and Toggle conditions, resulting in .
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10The Master-Slave JK Flip-Flop is designed primarily to eliminate:
A.Power consumption
B.Clock skew
C.Propagation delay
D.Race-around condition
Correct Answer: Race-around condition
Explanation:
By using two flip-flops (Master and Slave) clocked by complementary signals, the Master-Slave configuration prevents the output from changing more than once per clock cycle, effectively eliminating the race-around condition found in level-triggered JK flip-flops.
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11For a T Flip-Flop, the characteristic equation is:
A.
B.
C.
D.
Correct Answer:
Explanation:
In a T (Toggle) flip-flop, if , the state remains same (). If , the state toggles (). This behavior is described by the Exclusive-OR operation: .
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12How is a D Flip-Flop constructed using a JK Flip-Flop?
A.Connect to and to .
B.Connect to and to .
C.Connect to and to .
D.Connect both and to logic 1.
Correct Answer: Connect to and to .
Explanation:
To convert a JK flip-flop to a D flip-flop, we ensure the inputs are complementary. Setting and (using an inverter) ensures that when , the FF sets, and when , the FF resets.
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13In a NAND-based SR Latch, the 'active' state of the inputs is:
A.Clock Dependent
B.Active High
C.Edge Triggered
D.Active Low
Correct Answer: Active Low
Explanation:
A basic SR latch built with cross-coupled NAND gates operates with active-low inputs (often denoted as and ). Logic 0 activates the Set or Reset function.
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14Which table lists the required inputs for a given change of state?
A.Truth Table
B.Characteristic Table
C.Excitation Table
D.State Diagram
Correct Answer: Excitation Table
Explanation:
An Excitation Table shows the minimum input conditions required to generate a specific transition from a present state () to a next state ().
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15What are the excitation values () required to transition an SR flip-flop from to ?
A.
B.
C.
D.
Correct Answer:
Explanation:
To transition from 1 to 0, the flip-flop must be Reset. This requires and .
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16In a Master-Slave Flip-Flop, when is the output of the Slave flip-flop updated?
A.Continuously when the clock is high
B.On the rising edge of the clock (assuming positive edge triggered Master)
C.On the falling edge of the clock (assuming positive edge triggered Master)
D.Continuously when the clock is low
Correct Answer: On the falling edge of the clock (assuming positive edge triggered Master)
Explanation:
In a standard Master-Slave configuration, the Master is active during the positive clock phase, and the Slave is active during the negative clock phase (due to an inverter). The final output changes when the Slave captures the Master's data, which happens on the falling edge of the clock.
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17To convert a JK Flip-Flop into a T Flip-Flop, what connection is made?
A.Connect to and to
B.Connect Output to Input
C.Connect to
D.Connect and together to input
Correct Answer: Connect and together to input
Explanation:
A T flip-flop toggles when input is 1 and holds when input is 0. A JK flip-flop toggles when and holds when . By connecting and together to a single input , this behavior is achieved.
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18What is the result of the excitation table for a JK flip-flop for the transition ?
A.
B.
C.
D.
Correct Answer:
Explanation:
To go from 0 to 1, the JK flip-flop can either be Set () or Toggled (). In both cases, must be 1, and can be either 0 or 1 (Don't Care, X). Thus, .
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19If a T flip-flop is clocked with a frequency , what is the frequency of the output if is permanently connected to logic 1?
A.
B.
C.
D.
Correct Answer:
Explanation:
When , the flip-flop toggles on every active clock edge. It takes two clock cycles for the output to complete one full cycle (0 to 1 to 0). Therefore, the output frequency is half the clock frequency (). This constitutes a frequency divider.
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20What is the 'Setup Time' in the context of flip-flops?
A.The minimum time the input must remain stable after the active clock edge.
B.The time taken for the output to stabilize after the clock edge.
C.The minimum time the input must be stable before the active clock edge.
D.The pulse width of the clock signal.
Correct Answer: The minimum time the input must be stable before the active clock edge.
Explanation:
Setup time () is the minimum amount of time the data input must be held steady before the clock event so that the data is reliably sampled.
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21Which of the following is NOT a valid excitation for a D Flip-Flop?
A.If
B.If
C.If
D.If
Correct Answer: If
Explanation:
For a D flip-flop, . If the next state is 0, must be 0. Therefore, stating results in is incorrect.
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22The asynchronous inputs 'Preset' (PRE) and 'Clear' (CLR) on a flip-flop are used to:
A.Increase the clock frequency.
B.Convert the flip-flop from JK to SR.
C.Delay the output signal.
D.Set or Reset the flip-flop independently of the clock.
Correct Answer: Set or Reset the flip-flop independently of the clock.
Explanation:
Preset and Clear are direct (asynchronous) inputs that override the clock and synchronous inputs to force the flip-flop into a Set (1) or Reset (0) state immediately.
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23In a conversion from SR Flip-Flop to JK Flip-Flop, the logic expression for the input in terms of , , and is:
A.
B.
C.
D.
Correct Answer:
Explanation:
To simulate a JK flip-flop using an SR flip-flop: When (Set), we need . When (Toggle), if we need (Set), if we need (Reset). The mapping results in and .
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24What is the Hold Time?
A.Time for output to change.
B.Time after clock edge where data must remain stable.
C.Time before clock edge where data must be stable.
D.Time required for the clock to go from low to high.
Correct Answer: Time after clock edge where data must remain stable.
Explanation:
Hold time () is the minimum amount of time the data input must be held steady after the active clock edge to ensure the data is properly latched.
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25Which logic gate combination is commonly used to construct a Gated D Latch?
A.Two OR gates.
B.Two inverters only.
C.Four NAND gates.
D.One XOR gate.
Correct Answer: Four NAND gates.
Explanation:
A standard gated D latch is typically constructed using four NAND gates (or two AND gates, two NOR gates, and an inverter). The most common primitive representation uses 4 NANDs.
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26What is the primary disadvantage of an SR Flip-Flop compared to a JK Flip-Flop?
A.It consumes more power.
B.It has an invalid state when both inputs are 1.
C.It is slower.
D.It cannot be used in counters.
Correct Answer: It has an invalid state when both inputs are 1.
Explanation:
The primary logical disadvantage is that the input condition is forbidden/invalid in an SR flip-flop, whereas the JK flip-flop utilizes this combination to toggle the output.
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27When converting a T flip-flop to a D flip-flop, what is the required input equation for ?
A.
B.
C.
D.
Correct Answer:
Explanation:
We want . The T flip-flop equation is . So we need . XORing both sides with , we get .
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28Which triggering method is sensitive to the voltage level of the clock pulse?
A.Trailing Edge Triggering
B.Positive Edge Triggering
C.Negative Edge Triggering
D.Level Triggering
Correct Answer: Level Triggering
Explanation:
Level triggering allows the circuit to respond to inputs whenever the clock signal is at a specific voltage level (High or Low), as opposed to edge triggering which responds only to transitions.
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29The inputs to a master-slave JK flip-flop are . Assume the output is initially 0. After two full clock pulses, the output will be:
A.0
B.Indeterminate
C.1
D.High Impedance
Correct Answer: 0
Explanation:
With , the flip-flop toggles. Initially . After 1st pulse: . After 2nd pulse: .
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30In the excitation table of a T Flip-Flop, if and , what must be?
A.X (Don't Care)
B.0
C.1
D.High Z
Correct Answer: 1
Explanation:
The state has changed from 1 to 0 (toggled). For a T flip-flop to toggle, the input must be 1.
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31A negative edge-triggered flip-flop changes state when:
A.The clock goes from High to Low.
B.The clock is Low.
C.The clock is High.
D.The clock goes from Low to High.
Correct Answer: The clock goes from High to Low.
Explanation:
Negative edge triggering (or falling edge) occurs at the instant the clock signal transitions from logic 1 (High) to logic 0 (Low).
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32Which flip-flop is mathematically defined by assuming ?
A.T Flip-Flop
B.D Flip-Flop
C.SR Flip-Flop
D.JK Flip-Flop
Correct Answer: JK Flip-Flop
Explanation:
Start with JK equation: . If , then . The equation simplifies to .
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33To design a counter, which flip-flop is generally preferred due to its toggling capability?
A.T Flip-Flop (or JK in toggle mode)
B.SR Flip-Flop
C.Latch
D.D Flip-Flop
Correct Answer: T Flip-Flop (or JK in toggle mode)
Explanation:
Counters require the state to change (toggle) systematically. T Flip-Flops (or JK in toggle mode) are naturally suited for this because causes a toggle on every clock edge.
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34When converting an SR flip-flop to a T flip-flop, the inputs S and R are connected as:
A.
B.
C.
D.
Correct Answer:
Explanation:
We need the SR FF to toggle when . Toggling means if , set it (); if , reset it (). This logic implies and .
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35What happens to a D Latch when the Enable input is Low (0)?
A.The output holds the previous state.
B.The output sets to 1.
C.The output resets to 0.
D.The output follows the input D.
Correct Answer: The output holds the previous state.
Explanation:
When the Enable/Clock input of a D Latch is low (inactive), the latch is in the 'memory' or 'hold' state. Changes in D do not affect .
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36In digital electronics, the symbol '$ o$' in a state diagram represents:
A.An output variable.
B.An input variable.
C.A transition between states.
D.A static state.
Correct Answer: A transition between states.
Explanation:
Arrows in a state diagram represent transitions from one state to another, usually annotated with the input conditions causing that transition.
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37The simplified characteristic equation for a D flip-flop is:
A.
B.
C.
D.
Correct Answer:
Explanation:
The D flip-flop simply passes the value of input D to the output at the clock edge. Thus, the next state equals .
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38What is the minimum number of NAND gates required to implement a gated SR latch?
A.2
B.5
C.4
D.3
Correct Answer: 4
Explanation:
A basic SR latch uses 2 NAND gates. To add gating (Enable/Clock), 2 additional NAND gates are added to steer the inputs. Total = 4.
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39Which condition indicates a 'Hold' state in a JK flip-flop?
A.
B.
C.
D.
Correct Answer:
Explanation:
When both inputs and are 0, the JK flip-flop maintains its current state ().
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40If the setup time requirement of a flip-flop is violated, what is the likely outcome?
Violating setup or hold times can cause the flip-flop to enter a metastable state, where the output oscillates or hovers between logic levels for an indeterminate amount of time before settling randomly.
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41In the Master-Slave D Flip-Flop implementation, the Master is typically a:
A.JK Flip-Flop
B.T Flip-Flop
C.Gated D Latch
D.Counter
Correct Answer: Gated D Latch
Explanation:
A Master-Slave D Flip-Flop is constructed by cascading two Gated D Latches. The first is the Master (enabled by Clock) and the second is the Slave (enabled by inverted Clock).
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42Which of the following equations correctly represents the Reset condition of an SR flip-flop?
A.
B.
C.
D.
Correct Answer:
Explanation:
Reset means forcing the output to 0. In an SR flip-flop, this is achieved by making and .
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43When designing a sequential circuit using flip-flops, the first step is usually:
A.Selecting the power supply.
B.Drawing the logic diagram.
C.Writing VHDL code.
D.Creating a State Diagram or State Table.
Correct Answer: Creating a State Diagram or State Table.
Explanation:
The design process typically begins with defining the behavior of the system using a State Diagram or State Table, followed by state reduction, assignment, and finally deriving flip-flop input equations.
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44In a JK flip-flop, the 'Don't Care' condition in the excitation table appears in:
A.Neither column
B.Both J and K columns (depending on transition)
C.Only the K column
D.Only the J column
Correct Answer: Both J and K columns (depending on transition)
Explanation:
For , . For , . Thus 'Don't Care' (X) appears in both columns depending on the specific transition.
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45The propagation delay of a flip-flop is defined as:
A.Time between clock edge and output change.
B.Time between input change and output change.
C.Time between setup and hold.
D.Time required to power up.
Correct Answer: Time between clock edge and output change.
Explanation:
In synchronous circuits, propagation delay () is the time interval from the triggering edge of the clock signal to the stabilization of the new output state.
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46To convert a D Flip-Flop to a T Flip-Flop, the required input logic is:
A.
B.
C.
D.
Correct Answer:
Explanation:
We need the D flip-flop () to behave like a T flip-flop (). By equating the next states, we get .
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47Which of the following is true about asynchronous inputs?
A.They must respect setup times relative to the clock.
B.They affect the output immediately, regardless of the clock.
C.They are only available on latches, not flip-flops.
D.They are synchronized with the clock.
Correct Answer: They affect the output immediately, regardless of the clock.
Explanation:
Asynchronous inputs (Preset/Clear) override the clock signal and change the state of the flip-flop immediately upon activation.
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48What is the logic for input when converting a D flip-flop into a JK flip-flop? (Hypothetical conversion logic, though standard conversion is JK to D)
A.This requires external gates to map .
B.This conversion is not possible.
C.
D.
Correct Answer: This requires external gates to map .
Explanation:
To make a D flip-flop () behave like a JK (), we must drive the D input with the logic .
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49In a transparent D Latch, if Enable is High and D changes from 0 to 1 and back to 0, how does Q respond?
A.Q goes 0 to 1 and back to 0.
B.Q goes 0 to 1 and stays 1.
C.Q oscillates.
D.Q stays 0.
Correct Answer: Q goes 0 to 1 and back to 0.
Explanation:
Since the latch is transparent when Enable is High, the output follows the input in real-time. If pulses, pulses.
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50Which Flip-Flop is considered the most versatile and is available as a universal flip-flop in ICs?
A.SR Flip-Flop
B.JK Flip-Flop
C.D Flip-Flop
D.T Flip-Flop
Correct Answer: JK Flip-Flop
Explanation:
The JK flip-flop is considered the most versatile because it can function as a Set/Reset device, a Toggle device, or a Hold device, and can easily be converted into D or T flip-flops.
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