1Which of the following describes a sequential circuit used primarily to store and shift binary data?
A.Multiplexer
B.Counter
C.Decoder
D.Register
Correct Answer: Register
Explanation:
A register is a group of flip-flops used to store and shift binary data. While counters are sequential circuits, their primary purpose is counting pulses, whereas registers focus on storage and data movement.
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2In a 4-bit SISO (Serial-In Serial-Out) shift register, how many clock pulses are required to load 4 bits of data completely?
A.4
B.1
C.3
D.8
Correct Answer: 4
Explanation:
In a SISO register, data bits are entered one at a time. To load bits into an -bit register, clock pulses are required. Therefore, 4 pulses are needed for 4 bits.
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3Which type of shift register is the fastest for loading and retrieving data?
A.PISO
B.SIPO
C.PIPO
D.SISO
Correct Answer: PIPO
Explanation:
PIPO (Parallel-In Parallel-Out) is the fastest because data is loaded simultaneously into all flip-flops and transferred out simultaneously in a single clock pulse, unlike serial operations which require pulses.
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4What is the primary difference between a shift register and a counter?
A.A register moves data bits, while a counter progresses through a specific sequence of states.
B.A counter cannot store data.
C.A register uses logic gates only, while a counter uses flip-flops.
D.A register has no clock input.
Correct Answer: A register moves data bits, while a counter progresses through a specific sequence of states.
Explanation:
Registers are designed to store or shift data (left or right), whereas counters are designed to cycle through a predetermined sequence of binary numbers (states) based on input pulses.
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5To convert serial data to parallel data, which type of register is used?
A.PISO
B.PIPO
C.SISO
D.SIPO
Correct Answer: SIPO
Explanation:
A Serial-In Parallel-Out (SIPO) register accepts data serially (one bit at a time) and makes it available at the output pins simultaneously (in parallel), effectively performing serial-to-parallel conversion.
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6In a PISO (Parallel-In Serial-Out) shift register, the logical operation required to switch between loading data and shifting data is usually controlled by:
A.The Power supply
B.A Shift/Load control input
C.The Clock signal only
D.The Output buffer
Correct Answer: A Shift/Load control input
Explanation:
PISO registers typically use a combinational logic circuit at the input of the flip-flops controlled by a Shift/Load line to select whether new parallel data is loaded or existing data is shifted.
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7What is the minimum number of flip-flops required to construct a Mod-12 counter?
A.12
B.4
C.3
D.6
Correct Answer: 4
Explanation:
The number of flip-flops must satisfy the condition . For a Mod-12 counter (), (too small) and (sufficient). Thus, 4 flip-flops are required.
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8Which of the following is a characteristic of an Asynchronous Counter?
A.It requires more logic gates than a synchronous counter.
B.It is faster than a synchronous counter.
C.All flip-flops are clocked simultaneously.
D.The output of one flip-flop drives the clock of the next flip-flop.
Correct Answer: The output of one flip-flop drives the clock of the next flip-flop.
Explanation:
In asynchronous (ripple) counters, the external clock is applied only to the first flip-flop. Subsequent flip-flops are clocked by the output of the preceding flip-flop, causing a ripple effect.
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9A Universal Shift Register is capable of:
A.Shifting left only
B.Parallel loading only
C.Shifting right only
D.Shifting left, shifting right, and parallel loading
Correct Answer: Shifting left, shifting right, and parallel loading
Explanation:
A Universal Shift Register is a versatile circuit that can perform bidirectional shifts (left and right) and supports parallel input loading, making it capable of all basic register operations.
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10If a 4-bit ring counter is initialized with the value , what will be the state after 2 clock pulses?
A.
B.
C.
D.
Correct Answer:
Explanation:
A ring counter shifts the '1' in a circular fashion.
Initial: 1000
Pulse 1: 0100
Pulse 2: 0010.
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11What is the modulus of a 5-bit Johnson Ring Counter?
A.10
B.32
C.25
D.5
Correct Answer: 10
Explanation:
A Johnson counter (twisted ring counter) with flip-flops has distinct states. For a 5-bit counter, the modulus is .
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12In a synchronous counter, the propagation delay is:
A.Dependent on the number of flip-flops linearly
B.Zero
C.Accumulative (sum of all flip-flop delays)
D.Equal to the delay of a single flip-flop plus combinational gate delay
Correct Answer: Equal to the delay of a single flip-flop plus combinational gate delay
Explanation:
Since all flip-flops are clocked simultaneously in a synchronous counter, the total delay determines the maximum frequency and is roughly the propagation delay of one flip-flop plus the delay of the logic gates between stages, rather than the sum of all flip-flop delays.
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13Which problem is commonly associated with Asynchronous (Ripple) counters?
Because each flip-flop waits for the previous one to toggle, delays accumulate. This can cause temporary invalid states (glitches) at the output when decoding the count, limiting the maximum operating frequency.
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14To design a Mod-6 Asynchronous counter using 3 flip-flops, which logic gate is used to reset the counter?
A.AND gate
B.OR gate
C.NAND gate
D.NOT gate
Correct Answer: NAND gate
Explanation:
To create a Mod-6 counter (counting 0 to 5), the counter must reset when it hits binary 6 (). A NAND gate connected to the outputs representing 1s (Q2 and Q1) drives the active-low CLEAR/RESET inputs of the flip-flops.
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15How many states are unused in a 4-bit Ring Counter?
A.8
B.0
C.12
D.4
Correct Answer: 12
Explanation:
A 4-bit register has possible states. A basic Ring Counter uses only states (one-hot encoding). Therefore, the number of unused states is .
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16What is the maximum frequency of an -bit ripple counter with flip-flop propagation delay ?
A.
B.
C.
D.
Correct Answer:
Explanation:
For the counter to settle correctly before the next clock pulse, the clock period must be greater than the total accumulated delay (). Thus, .
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17Which shift register operation is equivalent to a multiplication by 2?
A.Circular Shift
B.Shift Left
C.Shift Right
D.Parallel Load
Correct Answer: Shift Left
Explanation:
In binary arithmetic, shifting bits to the left adds a zero at the Least Significant Bit (LSB) position, which effectively multiplies the binary number by 2 (e.g., becomes ).
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18For a 3-bit Synchronous Up-Counter using JK flip-flops, if the current state is , what is the next state?
A.000
B.100
C.111
D.010
Correct Answer: 100
Explanation:
An up-counter increments by 1. The binary sequence is (decimal 3). The next sequential number is decimal 4, which is .
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19What is the distinctive connection feature of a Johnson Counter?
A.The output of the first flip-flop is connected to the reset of the last.
B.The output of the last flip-flop is connected to the input of the first.
C.All flip-flops are connected to a common clock.
D.The inverted output of the last flip-flop is connected to the input of the first.
Correct Answer: The inverted output of the last flip-flop is connected to the input of the first.
Explanation:
A Johnson counter (or Switch-Tail Ring Counter) feeds the inverted output of the last stage back to the input of the first stage, creating a sequence of states.
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20A digital clock requires a seconds counter that counts from 0 to 59. This is essentially a:
A.Mod-60 Counter
B.Mod-100 Counter
C.6-bit Binary Counter
D.Mod-59 Counter
Correct Answer: Mod-60 Counter
Explanation:
A counter that counts distinct states (0 to ) is a Mod- counter. To count 0 to 59, there are 60 states, so it is a Mod-60 counter.
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21Which of the following describes the 'Lock-out' condition in counters?
A.The counter resets to zero prematurely.
B.The counter stops counting due to clock failure.
C.The counter outputs are all high.
D.The counter enters an unused state and cannot return to a valid state sequence.
Correct Answer: The counter enters an unused state and cannot return to a valid state sequence.
Explanation:
In counters with unused states (like Ring counters), if noise forces the counter into an unused state and the logic does not steer it back to the valid sequence, it is said to be in a 'Lock-out' condition.
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22How are flip-flops arranged in a 4-bit Asynchronous Down Counter?
A.Clock inputs are driven by outputs of previous stages.
B.Clock inputs are driven by outputs of previous stages (assuming negative edge trigger).
C.The inputs are connected to High logic.
D.All Clock inputs are connected to the main clock.
Correct Answer: Clock inputs are driven by outputs of previous stages (assuming negative edge trigger).
Explanation:
For a standard negative-edge triggered ripple counter, connecting the output to the next clock creates an UP counter. Connecting the output to the next clock creates a DOWN counter.
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23A bidirectional shift register uses:
A.Only JK flip-flops without logic gates
B.Combinational logic gates to route data from left or right
C.Only D flip-flops
D.Separate registers for left and right shifts
Correct Answer: Combinational logic gates to route data from left or right
Explanation:
To enable shifting in both directions, logic gates (multiplexers or AOI logic) are required at the inputs of the flip-flops to select whether the data comes from the left neighbor or the right neighbor.
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24If the input frequency to a Mod-16 counter is 16 kHz, what is the output frequency of the final stage?
A.256 kHz
B.1 kHz
C.4 kHz
D.16 kHz
Correct Answer: 1 kHz
Explanation:
Counters act as frequency dividers. The output frequency is . Here, .
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25Which type of counter is generally preferred for high-frequency applications?
A.Synchronous Counter
B.Ring Counter (without correction logic)
C.Asynchronous Counter
D.Ripple Counter
Correct Answer: Synchronous Counter
Explanation:
Synchronous counters are preferred for high speeds because all flip-flops change state simultaneously, eliminating the cumulative ripple delay found in asynchronous counters.
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26What is the sequence of states for a 3-bit Ring counter starting at 100?
A.100, 010, 001, 100...
B.100, 000, 100, 000...
C.100, 110, 111, 011...
D.100, 011, 010, 000...
Correct Answer: 100, 010, 001, 100...
Explanation:
A ring counter circulates a single '1'. For 3 bits, the pattern is 100 010 001 back to 100.
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27How many flip-flops are required to design a Mod-10 Ring Counter?
A.10
B.20
C.5
D.4
Correct Answer: 10
Explanation:
A Ring Counter is not a binary counter. It requires one flip-flop per state ( flip-flops for Mod-). Thus, a Mod-10 Ring Counter requires 10 flip-flops.
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28How many flip-flops are required to design a Mod-10 Binary Counter (BCD Counter)?
A.5
B.3
C.10
D.4
Correct Answer: 4
Explanation:
For a binary counter, . For , (too low) and (sufficient). So, 4 flip-flops are needed.
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29In a 4-bit synchronous counter design, the Excitation Table of the flip-flops is used to:
A.Determine the output delay
B.Reset the counter
C.Determine the required inputs (J, K or D) for a given state transition
D.Calculate the power consumption
Correct Answer: Determine the required inputs (J, K or D) for a given state transition
Explanation:
When designing synchronous counters, the excitation table is used to map current state () and next state () to the necessary flip-flop inputs to achieve that transition.
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30A 'Self-Correcting' counter is one that:
A.Uses error-correcting codes
B.Has no propagation delay
C.Automatically returns to a valid state sequence if it enters an invalid state
D.Resets to zero after every pulse
Correct Answer: Automatically returns to a valid state sequence if it enters an invalid state
Explanation:
Counters designed with unused states must ensure that if the system enters an unused state (due to noise), the next clock pulse(s) will eventually steer it back into the main counting loop.
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31What is the decimal equivalent range of a 5-bit binary counter?
A.1 to 32
B.0 to 5
C.0 to 31
D.0 to 15
Correct Answer: 0 to 31
Explanation:
A binary counter with bits counts from to . For , . The range is 0 to 31.
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32Which signal is necessary to load data into a shift register initially?
A.Clear
B.Clock
C.Output enable
D.Preset/Data Input
Correct Answer: Clock
Explanation:
While Preset/Data Inputs provide the value, the Clock signal is the triggering mechanism required to actually latch or shift the data into the flip-flops (unless using asynchronous Preset/Clear).
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33The decoding logic for a Ring counter is simpler than a Binary counter because:
A.It has more states
B.It uses fewer flip-flops
C.It requires no logic gates at all (outputs are directly available)
D.It operates at lower voltage
Correct Answer: It requires no logic gates at all (outputs are directly available)
Explanation:
In a Ring counter, each state is represented by a specific flip-flop being high (One-Hot). Therefore, no decoding gates are needed to determine which state the counter is in; you just read the output.
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34What happens in a SISO register if the data line is held High continuously while clocking?
A.The register fills with 1s
B.The register toggles
C.The register resets
D.The register fills with 0s
Correct Answer: The register fills with 1s
Explanation:
If the Serial Input is High (1), every clock pulse shifts a '1' into the first flip-flop and shifts existing 1s down the line. Eventually, the register contains all 1s.
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35A decade counter counts from:
A.1 to 10
B.0 to 10
C.0 to 9
D.0 to 100
Correct Answer: 0 to 9
Explanation:
A decade counter is a Mod-10 counter. It has 10 states, counting from 0 to 9, then resets to 0.
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36In a 4-bit PIPO register, if the parallel load input is active, the data appears at the output:
A.Immediately (Asynchronous load) or after 1 clock pulse (Synchronous load)
B.Never
C.After 2 clock pulses
D.After 4 clock pulses
Correct Answer: Immediately (Asynchronous load) or after 1 clock pulse (Synchronous load)
Explanation:
PIPO registers load all bits at once. Depending on design, this happens on the clock edge (synchronous) or immediately when the load control is asserted (asynchronous).
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37What is the main disadvantage of a Ring Counter compared to a Johnson Counter?
A.Cannot be preset
B.Complex decoding
C.Requires more flip-flops for the same number of states
D.Slower speed
Correct Answer: Requires more flip-flops for the same number of states
Explanation:
A Ring counter requires flip-flops for states. A Johnson counter requires only flip-flops for states (or FFs for states). Thus, Ring counters are less hardware efficient.
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38The sequence represents a:
A.3-bit Ring Counter
B.3-bit Binary Up Counter
C.3-bit Johnson Counter
D.Random Sequence Generator
Correct Answer: 3-bit Johnson Counter
Explanation:
A 3-bit Johnson counter sequence fills with 1s then fills with 0s: 000 001 011 111 110 100 000. (Note: The specific order depends on which end is MSB, but the pattern of filling 1s and 0s is characteristic).
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39Which flip-flop is commonly used to construct a T (Toggle) flip-flop for counters?
A.D Flip-Flop
B.RS Flip-Flop
C.Latch
D.JK Flip-Flop with J=1, K=1
Correct Answer: JK Flip-Flop with J=1, K=1
Explanation:
A JK flip-flop toggles its state on the clock edge when both J and K inputs are High (1). This is the standard way to implement the toggle action required for binary counters.
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40To create an -bit Synchronous Down Counter using T flip-flops, the input for the -th flip-flop (where ) should be driven by:
A.The clock signal
B.AND of all previous outputs
C.OR of all previous outputs
D.AND of all previous outputs
Correct Answer: AND of all previous outputs
Explanation:
In an Up counter, a bit toggles if all lower bits are 1. In a Down counter, a bit toggles if all lower bits are 0. Since is represented by , the logic requires the AND of all previous outputs.
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41What is the effect of propagation delay on the decoding of asynchronous counter states?
A.It has no effect
B.It improves accuracy
C.It generates decoding spikes (glitches)
D.It reduces power consumption
Correct Answer: It generates decoding spikes (glitches)
Explanation:
Because the bits change at slightly different times (ripple effect), the counter momentarily passes through intermediate, incorrect states. Decoders connected to these outputs may produce brief, false spikes (glitches).
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42If a 4-bit SISO register holds data '1010', and we shift right twice pushing in '0's, the new content is:
A.0101
B.1000
C.1010
D.0010
Correct Answer: 0010
Explanation:
Original: 1010.
Shift Right 1 (Input 0): 0101.
Shift Right 2 (Input 0): 0010.
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43Which application uses a counter to measure the duration of a signal?
A.Frequency Counter
B.Period/Time Interval Meter
C.Digital to Analog Converter
D.Digital Voltmeter
Correct Answer: Period/Time Interval Meter
Explanation:
By counting the number of known clock pulses that occur during the duration of the external signal (gating the clock), a counter measures the period or time interval.
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44In a 4-bit synchronous binary counter, the flip-flop representing the LSB (Least Significant Bit):
A.Toggles on every clock pulse
B.Toggles only when MSB is 1
C.Toggles when all other bits are 1
D.Never toggles
Correct Answer: Toggles on every clock pulse
Explanation:
In binary counting sequence (0, 1, 0, 1...), the LSB changes state on every single count/clock pulse.
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45What is the number of valid states in a 4-bit Johnson counter?
A.4
B.16
C.8
D.32
Correct Answer: 8
Explanation:
A Johnson counter has states. For , states.
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46Which statement is true regarding the hardware complexity of Synchronous vs Asynchronous counters?
A.Synchronous counters are simpler and use fewer gates.
B.They are identical in hardware.
C.Asynchronous counters are more complex.
D.Synchronous counters require more combinational logic (AND gates) for carry propagation.
Correct Answer: Synchronous counters require more combinational logic (AND gates) for carry propagation.
Explanation:
While synchronous counters are faster, they require additional logic gates to determine when upper bits should toggle (based on the state of lower bits), making the circuitry more complex than simple ripple connections.
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47How many clock pulses are needed to serially shift the binary number into a 4-bit SIPO shift register?
A.4
B.8
C.2
D.1
Correct Answer: 4
Explanation:
Regardless of whether it is SISO or SIPO, shifting 4 bits of data into the register serially requires 4 clock pulses.
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48Which register type is typically used for time delay generation?
A.Decoder
B.Multiplexer
C.PIPO
D.SISO
Correct Answer: SISO
Explanation:
A SISO register delays the data appearing at the output by clock cycles relative to the input. It is effectively a digital delay line.
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49An unused state in a Johnson counter (e.g., in a 3-bit counter) could be:
A.001
B.111
C.010
D.000
Correct Answer: 010
Explanation:
Valid 3-bit Johnson states are 000, 100, 110, 111, 011, 001. The states 010 and 101 are unused in the standard sequence.
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50What type of triggering is typically used in ripple counters to ensure proper counting?
A.Edge triggering
B.Static triggering
C.Pulse triggering
D.Level triggering
Correct Answer: Edge triggering
Explanation:
Counters rely on precise state transitions. Edge triggering (positive or negative) ensures the flip-flops toggle exactly at the transition of the clock pulse, preventing race conditions associated with level triggering.
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