Unit 3: Processing Data

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Processing is the stage where a computer accepts raw input, manipulates it inside the central processing unit (CPU), and returns meaningful output. Every device in this unit exists to move, store, or transform bits, so the whole chapter rests on one idea: computers only ever manipulate two-state electrical signals, and everything else is an interpretation layered on top.

I. Foundations of Data and Information

A computer is fundamentally a binary machine that senses whether a circuit is on or off and treats those two states as the digits 1 and 0.

Bit: the smallest unit, a single binary digit holding 0 or 1; it maps to one electrical state (voltage present / absent).
Byte: a group of 8 bits, the standard unit for one character; it yields 2⁸ = 256 possible patterns.
Word: the number of bits a CPU handles as a unit (commonly 32 or 64 bits); larger words move more data per operation.
Storage multiples: kilobyte (2¹⁰ bytes), megabyte (2²⁰), gigabyte (2³⁰), terabyte (2⁴⁰).
Von Neumann principle: both program instructions and data share the same memory and travel the same buses, which is why processing is a fetch-then-execute cycle.

II. Transforming Data into Information

From raw facts to usable meaning

The value of a computer lies in converting unorganised data into information a person can act on.

A. The information-processing model

Data: raw, unprocessed facts with no context: 48, 52, 50.
Processing: the operations applied — sorting, calculating, summarising, comparing.
Information: processed data given meaning: "average score = 50".
Feedback loop: output can become input for the next cycle, e.g. a running total updated with each new sale.

B. Stages of the transformation

Input: data enters via keyboard, sensor, or file.
Process: the CPU performs arithmetic and logic on it.
Output/Storage: results are displayed or saved for reuse.
- Quality dependence: information is only as good as its data — the "garbage in, garbage out" (GIGO) rule.

III. How Computers Represent Data

Encoding numbers, text and media as bits

All data types collapse to binary patterns before the CPU can handle them.

A. Number systems

Binary (base 2): uses digits 0–1; native to hardware.
Decimal to binary example: 13 → 1101 because 8 + 4 + 0 + 1 = 13.
Hexadecimal (base 16): a shorthand where one hex digit equals four bits, e.g. binary 1111 = hex F; compact for writing memory addresses.

B. Representing text

ASCII: 7- or 8-bit code covering 128/256 characters; the letter A is decimal 65, binary 01000001.
Unicode: extends encoding to over a million code points so scripts worldwide (e.g. Devanagari, emoji) each get a unique value; UTF-8 stores them in 1–4 bytes.

C. Representing other media

Images: a grid of pixels, each pixel storing colour as bits (24-bit colour = 8 bits each for red, green, blue).
Sound: sampled amplitude values recorded thousands of times per second (44,100 Hz for CD audio).
Common principle: analogue signals are digitised — measured at intervals and stored as numbers.

IV. How Computers Process Data

The CPU and its internal division of labour

Processing happens inside the microprocessor, a chip that coordinates fetching, decoding and executing instructions.

A. Components of the CPU

Control Unit (CU): directs the flow of data, fetches and decodes instructions, and signals other components when to act. It does no arithmetic itself.
Arithmetic Logic Unit (ALU): performs all calculations and comparisons.
- Arithmetic operations: add, subtract, multiply, divide.
- Logic operations: compare values using AND, OR, NOT, and tests like greater-than or equal-to.
Registers: tiny holding areas inside the CPU (detailed in Section VII).

B. Clock and processing speed

System clock: emits pulses at a fixed rate that synchronise every step; measured in hertz.
Clock speed: 1 GHz = one billion cycles per second; higher speed generally means more instructions per second.
Pipelining: overlapping stages of successive instructions so the ALU is not idle while the next instruction is being fetched.

V. Machine Cycles

The four-step rhythm behind every instruction

A machine cycle is the sequence the CPU repeats to carry out a single instruction, split into an instruction phase and an execution phase.

A. The four steps

TEXT

1. Fetch   - CU retrieves the next instruction from memory
2. Decode  - CU interprets what the instruction means
3. Execute - ALU performs the operation
4. Store   - result is written back to a register or memory

Instruction time (I-time): steps 1–2, fetching and decoding.
Execution time (E-time): steps 3–4, executing and storing.

B. Worked example

Adding two numbers stored in memory:

Fetch: CU loads the ADD instruction.
Decode: CU recognises it needs two operands.
Execute: ALU adds the values held in registers.
Store: the sum is placed back into a register.
Throughput link: MIPS (millions of instructions per second) measures how many such cycles complete each second.

VI. Memory

Working storage the CPU reads and writes directly

Memory holds instructions and data the CPU is currently using, distinct from long-term storage like a hard disk.

A. RAM (Random Access Memory)

Volatile: contents vanish when power is cut.
Read/write: the CPU can both store and retrieve from any address in roughly equal time ("random access").
Role: holds the active program and its data during execution.

B. ROM (Read Only Memory)

Non-volatile: retains contents without power.
Fixed content: written at manufacture; stores the boot/startup firmware (BIOS) that runs first when the machine powers on.

C. Memory addressing

Address: each byte-sized location has a unique number the CPU uses to find it.
Analogy: like numbered post-office boxes — the address locates the box, the contents are the stored value.
Capacity effect: more RAM lets more programs and larger data sets stay resident, reducing slow disk access.

VII. Registers

The fastest storage, inside the processor itself

Registers are small, high-speed storage locations within the CPU that hold the data and instructions being worked on right now.

A. Characteristics

Speed: fastest storage in the machine, accessed in a single clock cycle.
Size: measured in bits; register width (e.g. 64-bit) matches the CPU word size.
Capacity: very small — only a handful of values at a time.

B. Common register types

Accumulator: stores the intermediate result of ALU operations.
Instruction Register (IR): holds the instruction currently being decoded.
Program Counter (PC): holds the memory address of the next instruction to fetch.
Memory Address Register (MAR): holds the address being read from or written to.
Memory Data Register (MDR): holds the data in transit to or from memory.

VIII. The Bus

The electrical pathways that connect components

A bus is a set of parallel wires that carries bits between the CPU, memory and peripherals; its width and speed limit how fast data moves.

A. Types of bus

Data bus: carries the actual data; its width (e.g. 64 lines) sets how many bits transfer at once.
Address bus: carries the location of the data; its width fixes how much memory can be addressed. An n-line address bus reaches 2ⁿ locations, so 32 lines address 2³² ≈ 4 GB.
- Control bus: carries timing and command signals (read, write, clock) that coordinate the transfer.

B. Bus performance

Bus width: more lines = more bits per transfer, like more lanes on a road.
Bus speed (clock): measured in MHz; faster clocking pushes more transfers per second.
Expansion bus: connects add-in cards and peripherals (e.g. PCI Express) to the system.

IX. Cache Memory

A speed buffer between CPU and RAM

Cache is small, very fast memory that stores frequently or recently used data so the CPU avoids the slower trip to RAM.

A. Why cache exists

Speed gap: the CPU is far faster than RAM, so it would otherwise stall waiting for data.
Locality of reference: programs tend to reuse the same instructions and nearby data, so keeping them close pays off.
Cache hit / miss: a hit means the data was in cache (fast); a miss forces a fetch from RAM (slow).

B. Cache levels

L1: smallest and fastest, built into the CPU core.
L2: larger and slightly slower, on or near the core.
L3: largest and slowest of the three, often shared across cores.
Hierarchy principle: as you move outward — registers → L1 → L2 → L3 → RAM → disk — capacity grows but speed falls, and cost per byte drops. The system keeps the most-used data at the fastest, smallest level to balance cost against performance.