Unit 3: Processing Data - Practice Quiz

1 What is the term for raw, unprocessed facts and figures?

2 When data is processed and organized into a meaningful form, it becomes:

3 Which number system do computers use to represent data internally?

4 What is the smallest unit of data in a computer?

5 How many bits make up one byte?

6 Which coding standard is commonly used to represent characters using numbers?

7 Which component is often called the "brain" of the computer?

8 Which part of the CPU performs arithmetic and logical operations?

9 Which part of the CPU directs and coordinates the operations of the computer?

10 How many main steps are in a basic machine cycle?

11 Which step of the machine cycle retrieves an instruction from memory?

12 In the machine cycle, which step actually carries out the instruction?

13 Which type of memory loses its contents when the computer is turned off?

14 What does the abbreviation RAM stand for?

15 Which type of memory is non-volatile and typically stores startup instructions?

16 Where are registers located in a computer?

17 Compared to RAM, registers are:

18 What is the main function of a bus in a computer?

19 Which type of bus carries the actual data being transferred?

20 What is the main purpose of cache memory?

21 A retail store records every individual sale throughout the day. At closing, the manager runs a report showing total revenue, best-selling item, and average transaction value. Which statement best describes what happened in this scenario?

22 How many distinct values can be represented using a group of 6 bits?

23 A file is described as being 2 KB in size. Approximately how many bits does this represent (using bytes)?

24 A system uses a character encoding scheme that reserves 8 bits per character. What is the maximum number of unique characters this scheme can encode?

25 Which component of the CPU is responsible for performing arithmetic operations such as addition and logical comparisons?

26 What is the primary role of the Control Unit (CU) within the CPU?

27 In the correct order, what are the four steps of a standard machine (instruction) cycle?

28 Fetching and decoding an instruction are handled by one part of the CPU, while executing and storing are handled by another. Which pairing is correct?

29 A CPU has a clock speed of . Roughly how many clock cycles can it perform in one second?

30 A user notices that all open programs and unsaved documents disappear after a sudden power loss, but installed applications remain on the drive. Which characteristic of RAM explains the lost work?

31 Which type of memory holds the essential startup instructions (like the BIOS) and retains them even when the computer is turned off?

32 A computer with limited RAM begins using part of the hard drive to hold data that does not fit in RAM. What is this technique called?

33 Why are registers the fastest storage locations available to the CPU?

34 Which register holds the memory address of the next instruction to be fetched during the machine cycle?

35 During execution, the intermediate results of arithmetic operations performed by the ALU are commonly held in which register?

36 A CPU has a data bus that is 64 bits wide. What does this width primarily determine?

37 If a computer's address bus is 20 bits wide, how many unique memory addresses can it directly access?

38 Which bus is responsible for carrying signals that specify whether the CPU wants to read from or write to a memory location?

39 Why does adding cache memory typically improve overall system performance?

40 Ordering cache levels from fastest/smallest to slowest/largest, which sequence is correct?

41 A system stores unsigned integers in 8 bits. A program computes and stores the result in an 8-bit register. What value will the register hold after the operation?

42 Using two's complement in 8 bits, what is the decimal value of the bit pattern ?

43 In the standard machine cycle, which sequence correctly orders the phases the CPU performs for each instruction?

44 A processor has a 32-bit address bus. What is the maximum amount of directly addressable memory, assuming each address references one byte?

45 A CPU has a cache hit rate of . Cache access takes ns and main memory access takes ns. What is the average (effective) memory access time?

46 Which statement best explains why DRAM used as main memory requires periodic refreshing while SRAM used in cache does not?

47 During the fetch phase, which register holds the address of the next instruction to be retrieved, and which register receives the instruction once it arrives?

48 Two 4-bit signed (two's complement) numbers () and () are added. Why does this produce an incorrect result?

49 A memory bus runs at MHz and is bits wide. Assuming one transfer per clock cycle, what is its theoretical peak bandwidth?

50 In the data-to-information model, a temperature sensor logs the raw reading . Which action best represents transforming this data into information?

51 A designer wants to improve performance by adding an L2 cache between L1 cache and main memory. Which principle most directly justifies why this multi-level hierarchy reduces average access time?

52 A character encoded in ASCII occupies 7 significant bits. To represent the string "Data!" (5 characters) using 8-bit bytes, how many total bits are used?

53 A CPU without pipelining takes 4 clock cycles per instruction (one per machine-cycle phase) and runs at GHz. Approximately how many instructions can it execute per second?

54 Why can register access be roughly an order of magnitude faster than accessing L1 cache, despite both being fast on-chip storage?

55 The ALU performs a bitwise AND on and . What is the result?

56 A program runs with hit rate . Cache access is ns and memory access is ns. Below what hit rate does the effective access time exceed ns?

57 A system's data bus is 32 bits wide but its address bus is only 24 bits. What is the primary consequence of this configuration?

58 A student claims that adding more RAM always makes any program run faster. Under which condition is this claim least valid?

59 The hexadecimal value is stored in memory. What is its equivalent 8-bit binary and decimal representation?

60 In a pipelined CPU, the fetch, decode, execute, and store phases each take one cycle and different instructions occupy different phases simultaneously. Ideally, after the pipeline is full, how often does one instruction complete?