Unit 2: Oxidation process for semiconductors

1. Introduction to Silicon Oxidation

Silicon dioxide (SiO₂) is arguably the most critical material in silicon-based semiconductor manufacturing. Its formation through the process of oxidation is a fundamental step in creating integrated circuits (ICs). Thermal oxidation is the process of growing a thin, uniform, and high-purity layer of SiO₂ on a silicon wafer at high temperatures.

1.1 Purpose of SiO₂ in Semiconductor Devices

SiO₂ serves several crucial functions:

• Gate Dielectric: In a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a very thin, high-quality layer of SiO₂ acts as the insulating barrier between the metal gate and the silicon channel. The quality of this layer directly determines the transistor's performance and reliability.
• Surface Passivation: The silicon surface has "dangling bonds," which are electrically active and can trap charge, degrading device performance. Growing a layer of SiO₂ ties up these bonds, passivating the surface and making it electrically stable.
• Masking Layer: SiO₂ is highly resistant to dopant diffusion and etchants used in subsequent processing steps. It can be patterned using photolithography and etching to create windows, selectively introducing dopants (via ion implantation or diffusion) or etching underlying layers only in specific areas.
• Device Isolation: Thick layers of SiO₂, known as field oxides, are used to electrically isolate adjacent devices on the same chip, preventing current leakage and crosstalk. Techniques like LOCOS (Local Oxidation of Silicon) are based on this principle.

1.2 Desired Properties of SiO₂

• High dielectric strength (~10 MV/cm).
• High purity and low defect density.
• Excellent insulator with a large bandgap (~9 eV).
• Stable and reproducible Si/SiO₂ interface with low interface trap density.
• Ability to be etched controllably.
• Good barrier to dopants and impurities.

2. Types of Oxidation Techniques

2.1 Thermal Oxidation

This is the most prevalent method for growing high-quality SiO₂ for microelectronics. It involves heating silicon wafers to high temperatures (typically 900°C - 1200°C) in an environment containing an oxidizing species (oxidant). The silicon substrate itself is consumed during the process. For every 1 unit of silicon consumed, approximately 2.27 units of SiO₂ are formed due to the incorporation of oxygen and the lower density of SiO₂ compared to Si.

Thermal oxidation is further divided into two main categories:

• Dry Oxidation: Uses pure oxygen (O₂) as the oxidant.
• Wet Oxidation: Uses water vapor (H₂O) as the oxidant.

2.2 Other Techniques (Brief Overview)

While thermal oxidation is dominant, other specialized techniques exist:

• Plasma Enhanced Oxidation (or Anodization): Uses an oxygen plasma to create reactive oxygen species that oxidize the silicon surface. This can be done at much lower temperatures (300-600°C), which is beneficial for processing wafers with materials that cannot withstand high temperatures (e.g., metals like aluminum). The oxide quality is generally lower than thermal oxide.
• High-Pressure Oxidation (HiPOx): Thermal oxidation performed at high pressures (10-25 atm). The increased pressure raises the concentration of the oxidant at the oxide surface, significantly increasing the growth rate. This allows for the growth of thick oxides at lower temperatures, reducing the overall thermal budget and minimizing dopant diffusion.
• Electrochemical Anodization: An electrochemical cell is formed with the silicon wafer as the anode. When a current is passed, the silicon is oxidized. This is a room-temperature process but typically produces a porous, lower-quality oxide not suitable for most critical IC applications.

3. Silicon Oxidation Model: The Deal-Grove Model

The Deal-Grove model is the cornerstone for understanding and predicting the thermal oxidation of silicon. It describes the relationship between oxide thickness and oxidation time for thicknesses greater than ~20 nm.

3.1 Physical Process

The model assumes a three-step process for the oxidant to react with the silicon:

1. Mass Transfer: The oxidant species (O₂ or H₂O) is transported from the bulk of the furnace gas to the outer surface of the existing SiO₂ layer. The flux is given by F₁.
2. Diffusion: The oxidant diffuses through the existing SiO₂ layer to reach the Si/SiO₂ interface. The flux is given by F₂.
3. Reaction: The oxidant reacts with the silicon atoms at the Si/SiO₂ interface to form new SiO₂. The flux is given by F₃.

Under steady-state conditions, these three fluxes must be equal: F₁ = F₂ = F₃ = F.

3.2 Mathematical Formulation

The Deal-Grove model leads to the following general relationship:

X_o² + A * X_o = B * (t + τ)

Where:

• X_o: Thickness of the oxide layer.
• t: Oxidation time.
• A: A constant related to the reaction rate at the Si/SiO₂ interface.
• B: The parabolic rate constant, related to the diffusion of the oxidant through the oxide.
• τ (tau): A correction factor that accounts for the initial rapid oxidation phase or any pre-existing oxide layer.

The rate constants A and B are dependent on temperature, oxidant pressure, and crystal orientation.

3.3 Two Limiting Cases (Growth Regimes)

The general equation can be simplified into two distinct regimes based on the oxide thickness.

1. Linear Regime (Reaction-Rate Limited)

• Condition: For short times or thin oxides (t is small, X_o is small).
• Approximation: The X_o² term is negligible compared to the A * X_o term.
• Equation: A * X_o ≈ B * (t + τ) which simplifies to X_o ≈ (B/A) * (t + τ)
• Interpretation: The growth rate is constant and limited by the reaction rate at the Si/SiO₂ interface. The oxidant can diffuse through the thin oxide layer very quickly.
• B/A is known as the linear rate constant.

2. Parabolic Regime (Diffusion-Limited)

• Condition: For long times or thick oxides (t is large, X_o is large).
• Approximation: The A * X_o term is negligible compared to the X_o² term.
• Equation: X_o² ≈ B * t
• Interpretation: The growth rate slows down over time and is limited by the diffusion of the oxidant through the increasingly thick oxide layer. The reaction at the interface is instantaneous compared to the diffusion time.
• B is the parabolic rate constant.

3.4 Limitations of the Deal-Grove Model

The Deal-Grove model is highly successful but fails to accurately predict growth for very thin oxides (typically < 20 nm). In this region, an initial, much faster growth rate is observed than the model predicts. This "initial rapid growth regime" is attributed to factors not included in the model, such as space-charge effects, strain in the thin oxide, and a higher diffusion coefficient in the first few nanometers of SiO₂.

4. Dry and Wet Oxidation: A Comparison

The choice between dry and wet oxidation depends entirely on the desired properties and thickness of the final oxide film.

5. Factors Affecting Growth Mechanisms

Several physical parameters heavily influence the oxidation rate and the resulting oxide quality.

5.1 Temperature

• This is the most dominant factor. Both the linear (B/A) and parabolic (B) rate constants have a strong exponential dependence on temperature, following an Arrhenius relationship (Rate ∝ exp(-Ea / kT)).
• Effect: Higher temperatures dramatically increase the growth rate by providing more thermal energy for oxidant diffusion and the interface reaction.

5.2 Oxidant Partial Pressure

• The parabolic rate constant B is directly proportional to the partial pressure of the oxidant in the furnace.
• The linear rate constant B/A is also proportional to the partial pressure.
• Effect: Increasing the oxidant pressure increases the concentration of the oxidant at the oxide surface, which in turn increases the diffusion flux and thus the growth rate. This is the principle behind High-Pressure Oxidation (HiPOx).

5.3 Silicon Crystal Orientation

• The density of silicon atoms on the crystal surface varies with the crystallographic plane. The <111> plane is more densely packed with atoms than the <100> plane.
• Effect: The reaction rate is dependent on the number of available silicon bonds. Therefore, the linear rate constant (B/A) is larger for <111> silicon than for <100> silicon. The parabolic rate constant B is independent of orientation, as it relates to diffusion through the amorphous SiO₂.
• Result: Oxidation is faster on <111> wafers than on <100> wafers, especially in the linear regime.

5.4 Doping Concentration (Dopant Enhanced Oxidation - DEO)

• Heavily doped silicon oxidizes faster than lightly doped silicon. This effect is most pronounced for high concentrations (> 10¹⁹ cm⁻³) of phosphorus and boron.
• Effect: The dopants, particularly phosphorus, weaken the Si-Si bonds at the interface, making them easier to break and react with oxygen. They also increase the silicon vacancy concentration, which enhances the interface reaction.
• Result: Both the linear and parabolic rate constants increase with heavy doping. This can be problematic, leading to non-uniform oxide thickness over differently doped regions of a device.

6. Oxidation Induced Faults

While essential, the high-temperature oxidation process can introduce defects into the silicon crystal and alter device properties.

6.1 Oxidation-Induced Stacking Faults (OISF)

• A stacking fault is a disruption in the regular stacking sequence of crystallographic planes (e.g., ...ABCABCBABC...).
• Cause: During oxidation, the Si/SiO₂ interface is not a perfect sink for silicon atoms. About 0.1% of the silicon atoms consumed are injected back into the silicon substrate as silicon interstitials. An excess of these interstitials can condense to form an extra half-plane of atoms, creating a stacking fault.
• Impact: OISFs that cross a p-n junction can act as precipitation sites for metallic impurities and create leakage current paths, leading to device failure.

6.2 Dopant Redistribution

As the Si/SiO₂ interface moves into the silicon during oxidation, dopant atoms near the surface are redistributed. Their final location depends on their preference for silicon versus silicon dioxide.

• Segregation Coefficient (m): This is the ratio of the equilibrium concentration of the dopant in silicon to that in SiO₂ at the interface: m = C_Si / C_SiO₂.
  • m < 1 (e.g., Phosphorus, Arsenic): The dopant is more soluble in SiO₂. As the oxide grows, it takes up the dopant, leading to a pile-up of the dopant in the silicon just ahead of the advancing interface.
  • m > 1 (e.g., Boron): The dopant is more soluble in Si. The growing oxide rejects the dopant, causing it to diffuse away from the interface. This leads to depletion of the dopant in the silicon near the interface.
• Impact: Dopant redistribution alters the surface concentration, which can significantly change the threshold voltage (V_th) of a MOSFET and the characteristics of p-n junctions.

6.3 Interface Charges

The Si/SiO₂ interface is not perfectly neutral. Several types of charges can exist, which affect the electrical behavior of devices.

• Fixed Oxide Charge (Qf): A positive charge located within ~3 nm of the interface, caused by un-oxidized silicon ions.
• Mobile Ionic Charge (Qm): Positive ions like Na⁺, K⁺, which can move within the oxide under an electric field, causing device instability.
• Oxide Trapped Charge (Qot): Electrons or holes trapped in the bulk of the oxide, often due to radiation or hot carrier injection.
• Interface Trapped Charge (Qit): Charges located at the Si/SiO₂ interface due to structural defects or dangling bonds.

7. Thermal Oxidation Furnaces and RTP

7.1 Conventional Thermal Oxidation Furnaces

These systems are designed for batch processing, handling many wafers simultaneously to achieve high throughput.

• Configuration: Modern furnaces are typically vertical to minimize particle contamination and improve thermal uniformity across wafers compared to older horizontal designs.
• Components:
  • Quartz Tube: A high-purity fused quartz tube contains the processing environment.
  • Heating Elements: Resistive heating coils surround the tube, divided into multiple zones for precise temperature control.
  • Wafer Boat: Wafers stand vertically in a quartz or SiC carrier (boat).
  • Gas Control: Mass Flow Controllers (MFCs) precisely regulate the flow of O₂, N₂, H₂, and other gases.
  • Load Station: An automated system loads and unloads the wafer boat into the furnace.
• Process: Batch sizes can range from 25 to 200 wafers. The process involves slow temperature ramps, a long soak at the target temperature (hours), and a slow cool-down to prevent wafer warpage.

7.2 Rapid Thermal Processing (RTP)

RTP systems are used for single-wafer processing and are essential for controlling the thermal budget (D*t product, where D is diffusivity and t is time), which is critical for advanced, small-scale devices.

• Configuration: A single wafer is placed in a cold-wall quartz chamber.
• Components:
  • Heating Source: A bank of high-intensity tungsten-halogen lamps provides radiant heat.
  • Temperature Measurement: An optical pyrometer measures the wafer temperature directly.
  • Wafer Rotation: The wafer is rotated during processing to ensure temperature uniformity.
• Process:
  • Heating/Cooling: Extremely fast ramp rates (>100°C/s) are possible.
  • Time: Process times are very short, typically from seconds to a few minutes.
• Advantages:
  • Excellent Thermal Budget Control: Minimizes unwanted dopant diffusion.
  • Process Flexibility: The chamber can be used for different processes (oxidation, annealing, nitridation) by simply changing the gas and temperature profile.
• Applications: Ideal for forming ultra-thin gate oxides, annealing after ion implantation, and forming silicides.

8. Recent Trends in Oxidation

As transistors have shrunk, the classical SiO₂ gate dielectric has faced fundamental physical limits, leading to new materials and techniques.

8.1 Ultra-thin Gate Oxides and the Tunneling Limit

To maintain control over the channel in smaller transistors, the gate oxide thickness had to be scaled down. However, when SiO₂ thickness drops below ~1.5 nm, a quantum mechanical phenomenon called direct tunneling occurs, where electrons can pass directly through the thin insulator. This results in significant gate leakage current, which increases power consumption and degrades device reliability.

8.2 High-k Dielectrics

The solution to the tunneling problem was to replace SiO₂ with a material that has a higher dielectric constant (k).

• Principle: The capacitance of a gate is given by C = (k * ε₀ * A) / t.
• By using a material with a high k value, one can achieve the same capacitance with a physically thicker film. This thicker film effectively stops the tunneling leakage current.
• Equivalent Oxide Thickness (EOT): This metric is used to compare high-k dielectrics to SiO₂. EOT = (k_SiO₂ / k_high-k) * t_physical.
• Materials: Common high-k materials include hafnium oxide (HfO₂), hafnium silicate (HfSiO), and zirconium oxide (ZrO₂). These are now standard in advanced logic technologies (e.g., FinFETs).

8.3 Nitrided Oxides and Oxynitrides (SiON)

Incorporating nitrogen into the SiO₂ film creates silicon oxynitride (SiON). This is done by annealing the oxide in a nitrogen-containing ambient (e.g., NO, N₂O, NH₃).

• Benefits:
  • Increased Dielectric Constant: Nitrogen slightly increases the k-value (from ~3.9 for SiO₂ to ~4.5-5.5 for SiON).
  • Improved Reliability: The Si-N bond is stronger than the Si-H bond, making the dielectric more resistant to hot-carrier damage.
  • Diffusion Barrier: Nitrogen atoms accumulate at the Si/SiO₂ interface and act as an excellent barrier against dopant penetration, particularly boron from the polysilicon gate.

9. Doping and Implantation: Interaction with Oxidation

Oxidation and doping are not independent processes; they strongly influence one another.

9.1 Influence of Doping on Oxidation Rate

As covered in Section 5.4, heavy doping concentrations of phosphorus, arsenic, and boron enhance the oxidation rate. This must be accounted for in process modeling, as the oxide grown over a heavily doped source/drain region will be thicker than the oxide over a lightly doped channel region if they are oxidized simultaneously.

9.2 Influence of Oxidation on Dopant Profiles

Ion implantation introduces dopants into the silicon but also creates crystal damage. A subsequent high-temperature anneal is required to repair the damage and electrically "activate" the dopants. This anneal is often performed in an oxidizing ambient. This process is called drive-in oxidation.

• Consumption of Silicon: The growing oxide consumes the top layer of the implanted silicon. If the implant was very shallow, a significant fraction of the implanted dose could be lost into the oxide.
• Dopant Segregation: As the interface moves, dopants are redistributed according to their segregation coefficient (Section 6.2). Boron is depleted from the silicon surface, while phosphorus piles up.
• Diffusion: During the high-temperature oxidation step, the implanted dopants also diffuse deeper into the silicon substrate. The final junction depth is a result of this combined oxidation and diffusion process. Process engineers use sophisticated simulation tools (TCAD) to model and predict these complex interactions.