Back to Subject

Unit 6: Memory and Programmable Logic - Practice Quiz

ECE213 — Digital Electronics 60 Questions
0 Correct 0 Wrong 60 Left
0/60

1 What does the abbreviation ROM stand for?

Read-only memory Easy
A. Read-Only Memory
B. Rapid Onboard Memory
C. Read-Once Module
D. Random Output Memory

2 Which property best describes a ROM's data retention when power is removed?

Read-only memory Easy
A. It randomizes its data
B. It loses data (volatile)
C. It retains data (non-volatile)
D. It doubles its data

3 Which type of ROM can be erased using ultraviolet light?

Read-only memory Easy
A. EPROM
B. SRAM
C. PROM
D. Mask ROM

4 A ROM with address lines can store how many words?

Read-only memory Easy
A. 256 words
B. 512 words
C. 2048 words
D. 1024 words

5 What does RAM stand for?

Read/Write memory- SRAM and DRAM Easy
A. Read And Modify
B. Rapid Additive Memory
C. Read Access Memory
D. Random Access Memory

6 Which storage element is used by a static RAM (SRAM) cell?

Read/Write memory- SRAM and DRAM Easy
A. A flip-flop (latch)
B. A fuse link
C. A floating gate
D. A capacitor

7 Why does DRAM require periodic refreshing?

Read/Write memory- SRAM and DRAM Easy
A. Its capacitors leak charge over time
B. Its address lines overheat
C. Its fuses melt slowly
D. Its flip-flops reset randomly

8 Which memory type generally offers higher storage density per chip?

Read/Write memory- SRAM and DRAM Easy
A. PROM
B. DRAM
C. EPROM
D. SRAM

9 Which memory type is typically faster to access?

Read/Write memory- SRAM and DRAM Easy
A. EEPROM
B. SRAM
C. DRAM
D. Mask ROM

10 Both SRAM and DRAM share which common characteristic?

Read/Write memory- SRAM and DRAM Easy
A. They are non-volatile
B. They use UV erasure
C. They are volatile
D. They are read-only

11 What does the abbreviation PLA stand for?

PLAs and their applications Easy
A. Parallel Line Array
B. Portable Logic Adapter
C. Passive Logic Assembly
D. Programmable Logic Array

12 In a PLA, which arrays are programmable?

PLAs and their applications Easy
A. Only the OR array
B. Neither array
C. Only the AND array
D. Both the AND and OR arrays

13 A PLA is most commonly used to implement which type of logic?

PLAs and their applications Easy
A. Only analog filtering
B. Only clock generation
C. Combinational logic functions
D. Only power regulation

14 What does the abbreviation PAL stand for?

PALs and their applications Easy
A. Programmable Analog Line
B. Parallel Access Logic
C. Passive Array Latch
D. Programmable Array Logic

15 In a PAL device, which array is fixed (not programmable)?

PALs and their applications Easy
A. Both arrays
B. The input buffer array
C. The OR array
D. The AND array

16 Compared to a PLA, a key advantage of a PAL is that it is generally:

PALs and their applications Easy
A. Slower but more flexible
B. Analog-only
C. Non-programmable
D. Faster and simpler to program

17 What distinguishes a sequential PLD from a purely combinational PLD?

Sequential PLDs and their applications Easy
A. It cannot be programmed
B. It has no inputs
C. It includes memory elements such as flip-flops
D. It uses only resistors

18 Sequential PLDs are especially suitable for implementing which of the following?

Sequential PLDs and their applications Easy
A. Power supplies
B. Analog amplifiers
C. Finite state machines and counters
D. Pure resistor networks

19 What does the abbreviation FPGA stand for?

Introduction to field programmable gate arrays Easy
A. Field Powered General Array
B. Field Programmable Gate Array
C. Fixed Programmable Gate Adapter
D. Fast Parallel Gate Assembly

20 The basic reconfigurable logic building block inside a typical FPGA is called a:

Introduction to field programmable gate arrays Easy
A. Analog Sense Cell (ASC)
B. Configurable Logic Block (CLB)
C. Read-Only Block (ROB)
D. Central Processing Unit (CPU)

21 A ROM has 12 address lines and 8 data lines. What is the total storage capacity of this ROM?

Read-only memory Medium
A. bits
B. bits
C. bits
D. bits

22 A designer needs a ROM to implement a combinational circuit with 4 inputs and 3 outputs. What is the minimum ROM size required?

Read-only memory Medium
A.
B.
C.
D.

23 Which type of ROM can be electrically erased and reprogrammed byte-by-byte without removing it from the circuit?

Read-only memory Medium
A. UV-EPROM
B. PROM
C. Mask ROM
D. EEPROM

24 Why does DRAM require periodic refresh cycles while SRAM does not?

Read/Write memory- SRAM and DRAM Medium
A. DRAM operates at a higher voltage that decays
B. DRAM stores bits as charge on capacitors that leak over time
C. DRAM has fewer address lines than SRAM
D. DRAM uses flip-flops that lose state randomly

25 A typical six-transistor (6T) memory cell is characteristic of which memory technology?

Read/Write memory- SRAM and DRAM Medium
A. EEPROM
B. Flash ROM
C. SRAM
D. DRAM

26 For a given chip area, DRAM generally offers higher storage density than SRAM primarily because:

Read/Write memory- SRAM and DRAM Medium
A. SRAM cells store multiple bits each
B. Each DRAM cell needs far fewer components
C. DRAM does not need any address decoding
D. DRAM cells are made of larger capacitors

27 Which statement best describes why SRAM is typically used for cache memory rather than DRAM?

Read/Write memory- SRAM and DRAM Medium
A. SRAM is cheaper per bit than DRAM
B. SRAM has faster access times and needs no refresh
C. SRAM has higher density than DRAM
D. SRAM retains data without any power

28 In a PLA implementing Boolean functions, which arrays are programmable?

PLAs and their applications Medium
A. Only the OR array
B. Both the AND array and the OR array
C. Only the AND array
D. Neither array is programmable

29 A PLA has 3 inputs, 4 product terms, and 2 outputs. What is the maximum number of distinct product terms it can generate?

PLAs and their applications Medium
A. 4
B. 3
C. 2
D. 8

30 Two functions and are implemented in a PLA. How many unique product terms must the AND array provide?

PLAs and their applications Medium
A. 4
B. 5
C. 3
D. 2

31 Which advantage makes a PLA more area-efficient than a ROM for implementing sparse logic functions?

PLAs and their applications Medium
A. It stores every possible minterm permanently
B. It generates only the required product terms instead of all minterms
C. It uses fewer output lines than a ROM
D. It eliminates the need for input variables

32 What key component distinguishes a sequential PLD from a purely combinational PLD like a basic PLA?

Sequential PLDs and their applications Medium
A. Flip-flops (registers) at the outputs
B. Additional address decoders
C. A larger programmable OR array
D. More input buffers

33 A registered PLD output that can be fed back into the AND array is most useful for implementing:

Sequential PLDs and their applications Medium
A. Analog signal filters
B. Finite state machines
C. Purely resistive networks
D. Simple combinational decoders

34 In a typical macrocell of a sequential PLD, the output-select multiplexer is used to choose between:

Sequential PLDs and their applications Medium
A. SRAM and DRAM storage
B. Registered and combinational output modes
C. Input and clock signals
D. AND and OR array programming

35 A designer needs a device to implement a 3-bit synchronous counter. Which PLD feature is essential for this task?

Sequential PLDs and their applications Medium
A. On-chip clocked flip-flops
B. An analog comparator stage
C. Tri-state input buffers
D. A large ROM look-up table only

36 In an SRAM-based FPGA, the logic functionality of a configurable logic block is typically implemented using:

Introduction to field programmable gate arrays Medium
A. Look-up tables (LUTs)
B. Fixed NAND gate arrays
C. Fuse-programmed OR planes
D. Analog operational amplifiers

37 A 4-input LUT in an FPGA can implement any Boolean function of how many variables, and how many SRAM configuration bits does it require?

Introduction to field programmable gate arrays Medium
A. 8 variables, 16 bits
B. 16 variables, 4 bits
C. 4 variables, 4 bits
D. 4 variables, 16 bits

38 Why must most SRAM-based FPGAs be reconfigured each time power is applied?

Introduction to field programmable gate arrays Medium
A. Their routing is fixed at manufacture
B. Their configuration memory is volatile
C. Their clock circuits reset the logic gates
D. Their LUTs physically wear out on power-off

39 How does the internal structure of a PAL differ from that of a PLA?

PALs and their applications Medium
A. PAL has both arrays fixed
B. PAL has a programmable AND array and a fixed OR array
C. PAL has a fixed AND array and programmable OR array
D. PAL has both arrays programmable

40 In a PAL where each OR gate is hard-wired to exactly 3 product terms, what limits the implementation of a function requiring 5 product terms on one output?

PALs and their applications Medium
A. The volatility of the AND array
B. The number of programmable OR connections
C. The lack of any input buffers
D. The fixed number of product terms per OR gate

41 A ROM is used to implement combinational logic for a 4-input, 3-output function. Later, one output must be changed from to . What is the minimum modification required at the ROM level?

Read-only memory Hard
A. Only the stored word at address needs its corresponding output bit set to 1
B. An additional address line must be added to reach minterm 11
C. All 16 stored words must be rewritten because ROM contents are interdependent
D. The entire address decoder must be redesigned to accommodate the new minterm

42 A designer needs a ROM but only has ROM chips. How many chips are required and how are the address lines partitioned?

Read-only memory Hard
A. 4 chips; 9 lines address each chip and 2 higher-order lines select the chip via a decoder
B. 4 chips; 11 lines drive all chips in parallel with no decoding
C. 8 chips; 9 lines address each chip and 3 lines select the chip
D. 2 chips; 10 lines address each chip and 1 line selects the chip

43 A DRAM cell stores charge on a capacitor of . If leakage current is and the cell can tolerate a voltage drop of before data loss, what is the maximum refresh interval?

Read/Write memory- SRAM and DRAM Hard
A.
B.
C.
D.

44 In a 6-transistor SRAM cell, why is the cell susceptible to a read-disturb failure, and what parameter governs its stability during a read?

Read/Write memory- SRAM and DRAM Hard
A. The precharge phase overwrites the stored bit; the sense-amp gain governs stability
B. The refresh circuitry drains the storage node; the retention time governs stability
C. Access transistors briefly perturb the internal node voltage; the static noise margin (SNM) determines stability
D. The word line floats during read; the leakage current governs stability

45 A memory system uses DRAM with a refresh period and rows, using distributed refresh. What is the maximum time interval between consecutive refresh operations?

Read/Write memory- SRAM and DRAM Hard
A.
B.
C.
D.

46 A PLA has 4 inputs, 8 product terms, and 3 outputs. Two functions share the term . What is the primary advantage a PLA offers over a ROM for this implementation?

PLAs and their applications Hard
A. Product terms can be shared across outputs, so only the required minterms/implicants are programmed
B. The PLA automatically generates all minterms, guaranteeing full coverage
C. A PLA requires fewer address lines than an equivalent ROM
D. The PLA has a fixed OR array that reduces programming errors

47 Given and to implement on a PLA, what is the minimum number of product terms required if sharing is exploited?

PLAs and their applications Hard
A. 3 product terms: , ,
B. 4 product terms: , , ,
C. 5 product terms including all minterms
D. 2 product terms: ,

48 A PLA output is available in both true and complemented form via a programmable XOR. To implement with minimum product terms, which strategy is optimal?

PLAs and their applications Hard
A. Implement (2 terms) and program the XOR to invert the output
B. Implement all minterms of and disable the XOR
C. Implement the complement directly via its sum-of-products (4 terms)
D. Use two separate PLAs, one per product term

49 A registered PAL (e.g., 16R8) has all outputs fed back into the AND array. Why is this feedback essential for implementing a Moore finite-state machine?

Sequential PLDs and their applications Hard
A. It provides the current state to compute next-state and output logic within the same device
B. It refreshes the output registers to prevent data loss
C. It doubles the number of available product terms per output
D. It converts asynchronous inputs into synchronous ones automatically

50 A sequential PLD must implement a state machine with 12 states. What is the minimum number of state flip-flops (registered outputs) required, and how many unused states result?

Sequential PLDs and their applications Hard
A. 4 flip-flops; 4 unused states
B. 4 flip-flops; 12 unused states
C. 12 flip-flops; 0 unused states
D. 3 flip-flops; 5 unused states

51 In a GAL/registered PLD, the Output Logic Macrocell (OLMC) can be configured for combinational or registered output. What is the key benefit of this configurability over a fixed 16R8 architecture?

Sequential PLDs and their applications Hard
A. It allows the AND array to become programmable OR logic
B. Each output pin can independently be registered or combinational, increasing design flexibility
C. It permanently doubles the number of product terms available
D. It eliminates the need for a clock signal entirely

52 In an SRAM-based FPGA, a 4-input Look-Up Table (LUT) is used to implement combinational logic. How many distinct Boolean functions of 4 variables can a single 4-LUT realize?

Introduction to field programmable gate arrays Hard
A.
B.
C.
D.

53 Why do SRAM-based FPGAs require an external configuration memory (e.g., flash/PROM) at power-up, unlike antifuse or flash-based FPGAs?

Introduction to field programmable gate arrays Hard
A. The routing fabric is stored externally to save die area
B. SRAM cells can only be written once and need backup
C. SRAM configuration cells are volatile and lose their contents when power is removed
D. SRAM cells consume too much power to be programmed internally

54 A function requires 6 inputs but the FPGA has only 4-input LUTs. Using Shannon's expansion, what is the minimum number of 4-LUTs needed to decompose a general 6-input function (ignoring routing constraints)?

Introduction to field programmable gate arrays Hard
A. A single 4-LUT suffices by ignoring 2 inputs
B. 6 LUTs, one per input variable
C. Exactly 2 4-LUTs are always sufficient for any 6-input function
D. Split on 2 variables into 4 sub-functions plus multiplexing, needing several 4-LUTs cascaded

55 In FPGA architecture, what is the primary role of Configurable Logic Block (CLB) carry chains, and why are they dedicated rather than routed through general interconnect?

Introduction to field programmable gate arrays Hard
A. They implement the clock distribution network across the chip
B. They convert LUTs into block RAM when needed
C. They provide fast, low-skew ripple-carry paths for arithmetic, avoiding slow programmable routing delays
D. They store the configuration bitstream during power-up

56 What fundamentally distinguishes a PAL from a PLA in terms of programmable array structure, and how does it affect product-term sharing?

PALs and their applications Hard
A. Both arrays are programmable in a PAL, unlike a PLA
B. A PAL has a programmable AND array with a fixed OR array, so product terms cannot be shared across outputs
C. A PAL has no OR array, using only wired-AND logic
D. A PAL has a fixed AND array with a programmable OR array, allowing full sharing

57 A PAL device dedicates 4 product terms to each OR output. A required function is . What problem arises and what is the standard solution?

PALs and their applications Hard
A. The PAL automatically shares terms with another output to fit
B. The function is unimplementable on any PLD and requires a ROM
C. The function needs 5 product terms but only 4 are available; factor the function or use an output fed back as an input
D. Add a fifth input line to the AND array to gain a product term

58 When implementing a function on a PAL whose complement has fewer product terms than , and the PAL provides programmable output inversion, what is the best approach?

PALs and their applications Hard
A. Use a ROM instead because PALs cannot invert outputs
B. Split across two outputs and AND them externally
C. Implement in the AND-OR array and invert the output to obtain
D. Implement directly regardless, since inversion adds delay

59 A ROM-based lookup table is used to compute for a 4-bit input . What is the minimum ROM size (words × bits) needed to store all outputs without truncation?

Read-only memory Hard
A.
B.
C.
D.

60 Comparing SRAM and DRAM for the same storage capacity on identical process technology, which statement correctly captures the density-vs-speed trade-off?

Read/Write memory- SRAM and DRAM Hard
A. SRAM is denser because it needs no capacitor, while DRAM is faster due to fewer transistors
B. DRAM (1 transistor + 1 capacitor per cell) offers higher density but slower access and needs refresh; SRAM (6 transistors) is faster but less dense
C. DRAM is faster because the capacitor charges instantly, while SRAM latches slowly
D. Both have identical density; only power consumption differs
Previous MCQ
Unit 5