Unit 3: Introduction to Combinational Logic Circuits and Logic Families

I. Orientation: Combinational Logic and Logic Families

Combinational logic circuits produce outputs that depend only on the present combination of inputs, with no memory of past states (unlike sequential circuits). They are built entirely from logic gates and specified by a truth table, Boolean expression, or timing that ignores clocks. A logic family is the fabrication technology and circuit design style used to realise those gates, defining electrical behaviour like speed and power.

• Defining property: output = f(current inputs); no feedback storage element.
• Design flow: truth table → Boolean expression (SOP/POS) → minimisation (K-map/Boolean algebra) → gate network.
• Building blocks: AND, OR, NOT, plus universal gates NAND and NOR (any function realisable from either alone).
• Key family parameters: fan-in (inputs a gate accepts), fan-out (loads it drives), propagation delay t_pd, power dissipation, noise margin (tolerance to voltage disturbance).
• Convention: positive logic, HIGH = logic 1, LOW = logic 0.

II. Adders — Binary Addition Circuits

The point of an adder is to compute the arithmetic sum of binary numbers using only logic gates.

A. Half Adder

Adds two single bits and produces a sum and carry.

• Equations: for inputs A, B:
  
  TEXT

  Sum   = A ⊕ B
  Carry = A · B

• Symbols: ⊕ = XOR, · = AND. Sum is 1 when inputs differ; Carry is 1 only when both are 1.
• Limitation: cannot accept a carry from a lower stage, so it cannot be cascaded alone.

B. Full Adder

Adds three bits: two operands plus an incoming carry C_in.

• Equations:
  
  TEXT

  Sum    = A ⊕ B ⊕ C_in
  C_out  = A·B + C_in·(A ⊕ B)

• Construction: two half adders + one OR gate.
• Worked example: A=1, B=1, C_in=1 → Sum = 1⊕1⊕1 = 1, C_out = 1·1 + 1·0 = 1, giving binary 11 (decimal 3). Correct.
• Ripple-carry adder: n full adders chained, C_out of stage i feeds C_in of stage i+1; simple but delay accumulates across all stages.

III. Subtractors — Binary Subtraction Circuits

These compute the difference between binary numbers, tracking borrows instead of carries.

A. Half Subtractor

Subtracts one bit from another.

• Equations: for A − B:
  
  TEXT

  Difference = A ⊕ B
  Borrow     = A' · B

• Symbol: A' = NOT A. Borrow occurs only when A=0, B=1.

B. Full Subtractor

Subtracts B and an incoming borrow B_in from A.

• Equations:
  
  TEXT

  Difference = A ⊕ B ⊕ B_in
  Borrow_out = A'·B + B_in·(A ⊕ B)'... 

• Practical note: subtraction is usually done by addition of the 2's complement, so an adder with XOR-controlled inputs performs both add and subtract, saving hardware.

IV. Comparators — Magnitude Comparison Circuits

A comparator determines the relative magnitude of two binary numbers, asserting one of three outputs.

A. Magnitude Comparator

• Outputs: A>B, A=B, A<B (mutually exclusive).
• 1-bit equations:
  
  TEXT

  A=B : (A ⊙ B) = A'B' + AB   (XNOR)
  A>B : A·B'
  A<B : A'·B

• Multi-bit rule: compare most-significant bits first; equality propagates downward only while higher bits are equal. Equality overall requires all bit-pairs equal, i.e. the AND of all XNOR terms.
• Example device: the 7485 4-bit comparator has cascade inputs so several can chain for wider words.

V. Multiplexers and Demultiplexers — Data Routing Circuits

These select or distribute data lines under the control of select signals; they are duals of each other.

A. Multiplexers

A multiplexer (MUX) routes one of many inputs to a single output chosen by select lines.

• Size rule: 2ⁿ data inputs need n select lines. A 4-to-1 MUX uses 2 select lines S1 S0.
• 4-to-1 equation:
  
  TEXT

  Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3

• Symbols: I0–I3 data inputs, Y output, S select. The active product term passes exactly one input.
• Function generation: an n-select MUX implements any n-variable Boolean function by wiring 0/1 (or a literal) to each data input — a key application.

B. Demultiplexers

A demultiplexer (DEMUX) sends a single input to one of many outputs chosen by select lines.

• Size rule: 1 input, n select lines, 2ⁿ outputs.
• 1-to-4 equations: with input D:
  
  TEXT

  Y0 = S1'S0'·D   Y1 = S1'S0·D
  Y2 = S1S0'·D    Y3 = S1S0·D

• Relationship: a decoder with an enable input behaves as a DEMUX (the enable carries the data).

VI. Decoders — Code Conversion Circuits

A decoder activates exactly one of its outputs for each input code, expanding n coded lines into up to 2ⁿ output lines.

A. Line Decoder

• 2-to-4 example: inputs A, B → four minterm outputs:
  
  TEXT

  D0 = A'B'   D1 = A'B   D2 = AB'   D3 = AB

• Behaviour: for each input combination one output is HIGH (active-high) or LOW (active-low), the rest inactive.
• Applications: address decoding in memory, driving 7-segment displays (BCD-to-seven-segment decoder like the 7447), demultiplexing when enabled.
• Expansion: smaller decoders with enable lines combine to build larger ones.

VII. Encoders — Reverse Code Conversion Circuits

An encoder is the inverse of a decoder: it compresses 2ⁿ input lines into an n-bit code.

A. Priority Encoder

• Purpose: produces the binary code of an active input line.
• 8-to-3 encoder: 8 inputs → 3-bit output; only one input should be active in a plain encoder.
• Problem solved by priority version: if two inputs are HIGH simultaneously, a priority encoder outputs the code of the highest-priority active line and adds a valid-output flag.
• Example equation (priority, D7 highest):
  
  TEXT

  A2 = D4 + D5 + D6 + D7

  
  where A2 is the MSB of the output code.

VIII. Parity Circuits — Error-Detection Circuits

Parity circuits add or check a redundant bit so that single-bit errors in transmission can be detected.

A. Parity Generator and Checker

• Even parity: parity bit makes the total number of 1s even; generated by XOR of all data bits:
  
  TEXT

  P_even = D0 ⊕ D1 ⊕ D2 ⊕ D3

• Odd parity: invert the above (P_odd = XNOR chain); total 1s made odd.
• Checker: XOR of received data plus parity bit → error flag = 1 if parity violated.
• Example: data 1011 has three 1s; even-parity bit = 1⊕0⊕1⊕1 = 1, making 10111 with four 1s (even). Correct.
• Limitation: detects any odd number of bit errors but cannot detect an even number and cannot correct errors.

IX. Introduction to Different Logic Families

This section frames the technologies that physically implement all the above circuits and the criteria for comparing them.

A. Classification and Comparison Criteria

• Bipolar families: use BJTs — e.g. TTL, ECL. Generally faster, higher power.
• Unipolar families: use FETs — e.g. PMOS, NMOS, CMOS. Lower power, higher packing density.
• Comparison parameters:
  • Propagation delay: switching speed; ECL fastest, standard CMOS slower but improving.
  • Power dissipation: static + dynamic; CMOS lowest at low frequency.
  • Noise margin: difference between guaranteed output and required input levels; larger is more robust.
  • Fan-out: CMOS very high (capacitive load), TTL limited (~10).

X. Structure and Operations of TTL, MOS and CMOS Logic Families

This comparative section contrasts the three principal families named in the syllabus by structure and operation.

A. Structure and Operation of TTL

Transistor–Transistor Logic uses multi-emitter BJTs for input and a push-pull output.

• Input stage: a multi-emitter transistor performs the AND function on inputs.
• Totem-pole output: two stacked transistors give low output impedance and fast switching; only one conducts at a time.
• Levels: supply +5 V; V_OL ≈ 0.2 V, V_OH ≈ 3.4 V.
• Operation: grounding any emitter turns the input transistor on, steering current away from the phase splitter and driving output HIGH; all inputs HIGH gives LOW output — realising NAND.
• Trait: moderate speed, moderate power (~10 mW/gate), the 74xx series standard.

B. Structure and Operation of MOS Logic

MOS logic uses MOSFETs as switches, achieving high density and low power.

1. PMOS: p-channel devices, conduct with LOW gate; slower due to hole mobility; used in early calculators.
2. NMOS: n-channel devices, conduct with HIGH gate; roughly twice as fast as PMOS, used in early microprocessors.

• Load device: an ON MOSFET acts as the pull-up "resistor," saving chip area versus a diffused resistor.
• Advantage: small transistor footprint → high integration; drawback: static current flows in one logic state, wasting power.

C. Structure and Operation of CMOS

Complementary MOS pairs an NMOS and a PMOS network to combine the strengths of both.

• Structure: PMOS pull-up network connects output to V_DD; complementary NMOS pull-down network connects output to ground.
• Operation: for any input, exactly one network conducts, so the output is firmly HIGH or LOW and no direct V_DD-to-ground path exists in steady state.
• Static power: near zero — dissipation is dynamic, proportional to frequency, load capacitance and V_DD² (P ≈ C·V_DD²·f).
• Traits: wide supply range, high noise margin, very high fan-out, dominant in modern VLSI.
• Inverter example: input HIGH turns NMOS on and PMOS off → output LOW; input LOW reverses it → output HIGH, drawing no static current in either state.