Unit 4: Introduction to Sequential Logic Circuits

Sequential logic circuits are digital circuits whose outputs depend not only on the present inputs but also on the past sequence of inputs, stored as internal state. Unlike combinational circuits, they contain memory elements and feedback, and they form the basis of registers, counters and memory. The elementary memory element is the bistable — a circuit with two stable states, 0 and 1 — realised as latches (level-controlled) and flip-flops (edge/pulse-controlled).

I. Orientation: Foundations of Sequential Logic

Sequential logic is built on feedback and clocking, where a stored bit is held until a control signal permits change.

• Memory via feedback: Cross-coupling two NAND or NOR gates so each gate's output feeds the other's input; this creates a self-sustaining loop that holds one bit indefinitely.
• State variable Q: The output Q denotes the stored bit; Q' (or Q̄) is its complement. A well-formed bistable always keeps Q and Q' opposite.
• Present vs next state: Analysis uses present state Qₙ and next state Qₙ₊₁; the characteristic equation expresses Qₙ₊₁ in terms of inputs and Qₙ.
• Latch vs flip-flop: A latch is level-sensitive — it responds whenever its enable/clock is at the active level. A flip-flop is edge/pulse-triggered — it responds only at a clock transition, giving synchronous operation.
• Excitation vs characteristic: The characteristic table gives output from inputs; the excitation table works backwards, giving the inputs required to force a desired state transition (used in design and conversion).
• Invalid/forbidden condition: Some devices have an input combination that violates Q ≠ Q'; designs must avoid or override it.

II. The SR Latch — Set–Reset Bistable

The SR latch is the simplest one-bit memory, controlling storage through separate Set and Reset lines.

A. Definition and Structure

• Set and reset: Asserting S drives Q=1; asserting R drives Q=0; with both inactive it holds the last value.
• NOR implementation: Two cross-coupled NOR gates, active-HIGH inputs.

Q  = (R + Q')'
Q' = (S + Q )'

• NAND implementation (S'R' latch): Two cross-coupled NAND gates, active-LOW inputs; the hold state is S'=R'=1.

B. Characteristic Behaviour

• Truth table (active-HIGH NOR):

S R | Qₙ₊₁
0 0 | Qₙ   (hold)
0 1 | 0    (reset)
1 0 | 1    (set)
1 1 | ---  (forbidden)

• Forbidden state: S=R=1 forces both outputs to 0, breaking Q ≠ Q'; on release, the final state is unpredictable (race). This is the SR latch's key limitation.
• Characteristic equation: Qₙ₊₁ = S + R'Qₙ, valid when SR = 0.

C. Gated (Enable) SR Latch

• Purpose: Add an Enable/clock input so the latch changes only while EN=1, decoupling data timing from arrival.
• Structure: AND S and R each with EN before feeding the cross-coupled pair; when EN=0 the latch holds regardless of S, R.

III. The D Latch — Data / Transparent Latch

The D latch removes the forbidden state by ensuring the Set and Reset inputs are always complementary.

A. Definition and Structure

• Single data input: One input D feeds S, and its inverse feeds R, so S and R can never both be 1.
• Enable control: Uses a gated structure; when EN=1 the latch is transparent (Q follows D); when EN=0 it latches the last value.

B. Characteristic Behaviour

• Truth table:

EN D | Qₙ₊₁
1  0 | 0
1  1 | 1
0  X | Qₙ (hold)

• Characteristic equation: Qₙ₊₁ = D (while enabled).
• Transparency hazard: Because it is level-sensitive, any change in D while EN=1 passes straight through — undesirable in synchronous systems, motivating the flip-flop.

IV. The D Flip-Flop — Edge-Triggered Data Store

The D flip-flop captures the data input at a single clock edge, giving deterministic synchronous storage of one bit.

A. Definition and Structure

• Edge capture: Samples D only at the active clock edge (e.g. rising); between edges the output is frozen.
• Realisation: Commonly two D latches in a master–slave arrangement or a dedicated edge-triggered cell.

B. Characteristic Behaviour

• Characteristic equation: Qₙ₊₁ = D, applied at the clock edge only.
• Data delay: Output at edge n+1 equals the input sampled at edge n, so a chain of D flip-flops behaves as a shift register, moving one bit per clock.

V. The JK Flip-Flop — Universal Toggling Flip-Flop

The JK flip-flop refines SR by turning the forbidden combination into a useful toggle operation.

A. Definition and Structure

• J and K: J acts like Set, K like Reset, but J=K=1 toggles instead of being illegal.
• Feedback: Achieved by feeding Q and Q' back into the input gates so J is gated with Q' and K with Q.

B. Characteristic Behaviour

• Truth table:

J K | Qₙ₊₁
0 0 | Qₙ   (hold)
0 1 | 0    (reset)
1 0 | 1    (set)
1 1 | Qₙ'  (toggle)

• Characteristic equation: Qₙ₊₁ = JQₙ' + K'Qₙ.
• Race-around problem: In a level-triggered JK with J=K=1, the output toggles repeatedly while the clock is high (if the pulse width exceeds the propagation delay), leaving the final state uncertain. This is solved by edge triggering or master–slave construction.

VI. The T Flip-Flop — Toggle Flip-Flop

The T flip-flop provides a single-input device that either holds or inverts its state, ideal for frequency division and counting.

A. Definition and Structure

• Single toggle input: T=0 holds; T=1 complements the stored bit at the clock edge.
• Derivation: Formed by tying together the two inputs of a JK flip-flop (J=K=T).

B. Characteristic Behaviour

• Characteristic equation: Qₙ₊₁ = TQₙ' + T'Qₙ = T ⊕ Qₙ.
• Frequency division: With T held at 1, Q toggles every clock edge, so its frequency is half the clock — a divide-by-2 stage; cascading n stages divides by 2ⁿ.

VII. Conversion of Basic Flip-Flops

Any flip-flop can be built from another by adding combinational logic driven by the excitation requirements of the target device.

A. Method

• Procedure: State the desired flip-flop's characteristic/excitation table, list the available flip-flop's excitation table, map required inputs against Qₙ→Qₙ₊₁, then simplify with a K-map to get input equations.
• Excitation tables (key data):

SR: 0→0 S=0,R=X   JK: 0→0 J=0,K=X
    0→1 S=1,R=0       0→1 J=1,K=X
    1→0 S=0,R=1       1→0 J=X,K=1
    1→1 S=X,R=0       1→1 J=X,K=0
D : Qₙ₊₁=D         T : T=Qₙ⊕Qₙ₊₁

B. Representative Conversions

1. JK → D: Force J=D, K=D'; a single inverter suffices, giving Qₙ₊₁ = D.
2. D → JK: Feed D = JQ' + K'Q (the JK characteristic equation) into the D input, reconstructing JK behaviour.

• SR → JK: S = JQ', R = KQ — the feedback that removes the forbidden state.
• JK → T: Tie J=K=T, yielding Qₙ₊₁ = T ⊕ Qₙ.
• D → T: D = T ⊕ Qₙ, using an XOR of T with the fed-back output.

VIII. Master–Slave Flip-Flop

The master–slave configuration eliminates the race-around problem by splitting one clock period into two isolated transfer phases.

A. Structure and Operation

• Two cascaded latches: A master latch clocked by CLK and a slave latch clocked by CLK' (inverted), so the two are never transparent simultaneously.
• Two-phase transfer:
  • CLK=1: Master accepts inputs; slave is isolated and holds the old output.
  • CLK=0: Master is isolated; slave copies the master's value to the output.
• Effect: Data is sampled once and transferred once per full clock cycle, so J=K=1 toggles exactly once — no race-around.

B. Behaviour and Limitation

• Pulse triggering: Effectively behaves like a flip-flop responding to a complete clock pulse (level, not a true edge).
• Ones-catching: A momentary 1 on J (or K) while CLK=1 can be "caught" by the master and wrongly transferred; true edge-triggered designs avoid this.

IX. Edge Triggering

Edge triggering makes a flip-flop respond only during the brief instant of a clock transition, giving precise synchronous timing.

A. Principle and Types

• Edge detection: A differentiator or gate network produces a narrow spike at the clock transition, enabling data capture only then.
• Two variants:
  1. Positive-edge triggered: Responds on the LOW→HIGH transition (shown by a > clock symbol).
  2. Negative-edge triggered: Responds on the HIGH→LOW transition (shown by > with an inversion bubble).

B. Significance

• Timing parameters: Requires setup time (data stable before the edge) and hold time (data stable after the edge) to latch correctly; violation causes metastability.
• Advantage over level triggering: Because the active window is momentarily short, inputs may change freely between edges without corrupting the state, which is essential for reliable registers, counters and shift registers.