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Unit 3: Introduction to Combinational Logic Circuits and Logic Families - Practice Quiz

ECE213 — Digital Electronics 60 Questions
0 Correct 0 Wrong 60 Left
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1 How many inputs does a half adder have?

Adders Easy
A. 1
B. 4
C. 3
D. 2

2 The Sum output of a half adder is generated using which logic gate?

Adders Easy
A. AND gate
B. XOR gate
C. OR gate
D. NAND gate

3 A full adder adds how many input bits together?

Adders Easy
A. Five bits
B. Two bits
C. Three bits
D. Four bits

4 The difference output of a half subtractor is produced by which gate?

Subtractors Easy
A. AND gate
B. NOR gate
C. XOR gate
D. OR gate

5 In a half subtractor, the borrow output is generated when:

Subtractors Easy
A. and
B. and
C. and
D. and

6 A digital comparator is used to:

Comparators Easy
A. Add two binary numbers
B. Store binary data
C. Compare two binary numbers
D. Convert binary to decimal

7 How many output conditions does a magnitude comparator typically produce?

Comparators Easy
A. One (equality only)
B. Three (, , )
C. Four
D. Two (, )

8 A multiplexer (MUX) performs which function?

Multiplexers and Demultiplexers Easy
A. Stores multiple bits
B. Selects one of many inputs to a single output
C. Adds multiple inputs together
D. Splits one input into many outputs

9 How many select lines are required for an multiplexer?

Multiplexers and Demultiplexers Easy
A. 4
B. 8
C. 3
D. 2

10 A demultiplexer (DEMUX) performs which function?

Multiplexers and Demultiplexers Easy
A. Generates a parity bit
B. Compares two numbers
C. Routes one input to one of many outputs
D. Combines many inputs into one output

11 A -to- line decoder has how many output lines?

Decoders Easy
A. 3
B. 16
C. 6
D. 8

12 The main function of a decoder is to:

Decoders Easy
A. Convert coded input into a unique output
B. Add two binary numbers
C. Combine multiple outputs into one
D. Compare two inputs

13 An encoder performs the opposite operation of which circuit?

Encoders Easy
A. Comparator
B. Decoder
C. Flip-flop
D. Adder

14 How many input lines does an -to- encoder have?

Encoders Easy
A. 4
B. 3
C. 8
D. 16

15 A parity bit is added to data primarily for:

Parity circuits Easy
A. Data encryption
B. Error detection
C. Faster processing
D. Data compression

16 Which gate is commonly used to generate a parity bit?

Parity circuits Easy
A. AND gate
B. OR gate
C. XOR gate
D. NOT gate

17 Which of the following is a bipolar logic family?

Introduction to different logic families Easy
A. CMOS
B. PMOS
C. TTL
D. NMOS

18 CMOS logic uses which type of transistors?

Structure and operations of TTL, MOS and CMOS logic families Easy
A. Both NMOS and PMOS
B. Only bipolar junction transistors
C. Only NMOS
D. Only PMOS

19 Which logic family is known for the lowest static power consumption?

Structure and operations of TTL, MOS and CMOS logic families Easy
A. CMOS
B. TTL
C. ECL
D. DTL

20 The basic building block of TTL logic is the:

Structure and operations of TTL, MOS and CMOS logic families Easy
A. Diode only
B. MOSFET
C. Vacuum tube
D. Bipolar junction transistor (BJT)

21 A full adder adds three input bits , , and . What is the sum and carry-out when , , and ?

Adders Medium
A. Sum , Carry
B. Sum , Carry
C. Sum , Carry
D. Sum , Carry

22 To construct a 4-bit ripple carry adder, how many full adders are required?

Adders Medium
A.
B.
C.
D.

23 The main disadvantage of a ripple carry adder compared to a carry look-ahead adder is:

Adders Medium
A. Simpler carry generation
B. More power efficiency
C. Higher propagation delay
D. Fewer logic gates

24 In a full subtractor computing , what are the Difference and Borrow when , , and ?

Subtractors Medium
A. Difference , Borrow
B. Difference , Borrow
C. Difference , Borrow
D. Difference , Borrow

25 A full adder can be converted into a full subtractor (using 2's complement) by:

Subtractors Medium
A. Adding a NOT gate at the sum output only
B. Inverting the minuend bits and setting
C. Inverting the subtrahend bits and setting
D. Inverting both inputs and setting

26 A 1-bit magnitude comparator outputs , , and . What is the logic expression for the output?

Comparators Medium
A.
B.
C.
D.

27 For two 4-bit numbers, how many comparison outputs (, , ) does a standard magnitude comparator produce?

Comparators Medium
A.
B.
C.
D.

28 When comparing two 4-bit numbers and , which output of the comparator is high?

Comparators Medium
A.
B.
C. None of the outputs
D.

29 How many select lines are required for a 16-to-1 multiplexer?

Multiplexers and Demultiplexers Medium
A.
B.
C.
D.

30 A demultiplexer with 3 select lines can route a single input to how many output lines?

Multiplexers and Demultiplexers Medium
A.
B.
C.
D.

31 To implement a Boolean function of 3 variables using a single multiplexer with the variables on the select lines, what size multiplexer is needed?

Multiplexers and Demultiplexers Medium
A. -to-1
B. -to-1
C. -to-1
D. -to-1

32 A 3-to-8 line decoder activates how many output lines at a time for a given valid input?

Decoders Medium
A.
B.
C.
D.

33 How many 2-to-4 decoders (with enable) are needed to build a 4-to-16 decoder?

Decoders Medium
A.
B.
C.
D.

34 A BCD-to-7-segment decoder is primarily used to:

Decoders Medium
A. Perform arithmetic addition
B. Drive display segments for decimal digits
C. Convert binary to Gray code
D. Generate parity bits

35 In a priority encoder, when multiple inputs are active simultaneously, the output corresponds to:

Encoders Medium
A. The highest-priority active input
B. An undefined value
C. The lowest-priority active input
D. The sum of all active inputs

36 An octal-to-binary (8-to-3) encoder has how many output lines?

Encoders Medium
A.
B.
C.
D.

37 For the 7-bit data word , what even parity bit should be appended?

Parity circuits Medium
A.
B. Cannot be determined
C.
D.

38 Which gate is fundamental to building parity generator and checker circuits?

Parity circuits Medium
A. AND gate
B. XOR gate
C. NAND gate
D. OR gate

39 Which characteristic best describes CMOS logic compared to TTL?

Structure and operations of TTL, MOS and CMOS logic families Medium
A. Very low static power consumption
B. Faster switching in all conditions
C. Lower noise margin
D. Higher static power consumption

40 A standard TTL NAND gate uses which device at its input stage?

Structure and operations of TTL, MOS and CMOS logic families Medium
A. A single MOSFET
B. A multi-emitter bipolar transistor
C. A Schottky diode array
D. A pair of complementary FETs

41 A ripple-carry adder is built from full adders each having a propagation delay of for both sum and carry outputs. For an -bit adder, the worst-case time to produce a valid final sum is best approximated by:

Adders Hard
A.
B.
C.
D.

42 In a carry-lookahead adder, the block generate and block propagate for two bits are defined using and . The group carry-out (with carry-in ) equals:

Adders Hard
A.
B.
C.
D.

43 A 4-bit adder/subtractor uses XOR gates and a mode line ( for subtraction) feeding . When computing in 2's complement, an overflow for signed numbers is detected by:

Subtractors Hard
A.
B.
C.
D. alone

44 Using 2's complement in a 4-bit subtractor to compute (unsigned inputs), the result bits and the borrow/carry-out are:

Subtractors Hard
A. Result , carry-out (no borrow)
B. Result , carry-out
C. Result , carry-out
D. Result , carry-out (borrow occurred)

45 For a 1-bit magnitude comparator with inputs and , the output is and is . When cascading to compare multi-bit numbers, the overall output for two bits ( vs ) is:

Comparators Hard
A.
B.
C.
D.

46 An IC 7485 4-bit comparator has cascading inputs. To correctly cascade multiple 7485s, the cascading inputs of the least-significant stage must be set to:

Comparators Hard
A. respectively
B. respectively
C. respectively
D. respectively

47 A function is implemented using an 8:1 MUX with as select lines. If , the data inputs through must be:

Multiplexers and Demultiplexers Hard
A. , rest
B. , rest
C. All inputs
D. , rest

48 To realize using an 8:1 MUX with as selects and available, the input (select , i.e., ) should be connected to:

Multiplexers and Demultiplexers Hard
A.
B.
C.
D.

49 A demultiplexer is built by cascading two demultiplexers. The minimum number of additional select and enable connections required is best described as:

Multiplexers and Demultiplexers Hard
A. Two extra select bits and two enables
B. One extra enable only, no new select bit
C. One extra select bit driving the two enables (via true/complement)
D. Four extra select bits

50 An active-low output decoder with an active-high enable is used to implement . Since outputs are active-low, the correct gate to combine the relevant decoder outputs is:

Decoders Hard
A. An OR gate over outputs
B. A NAND gate over outputs
C. An AND gate over outputs
D. A NOR gate over outputs

51 A BCD-to-7-segment decoder receives an invalid input (decimal 10). In a typical non-ripple-blanking decoder without explicit handling of invalid codes, the segment outputs are:

Decoders Hard
A. Always all segments OFF
B. Undefined/don't-care unless the design specifies otherwise
C. Guaranteed to display the digit 0
D. Always all segments ON

52 In an 8-to-3 priority encoder, inputs are active with and all others 0. Assuming highest-index priority, the 3-bit output and valid bit are:

Encoders Hard
A. , valid
B. , valid
C. , valid
D. , valid

53 Why is a plain (non-priority) -to- encoder unsuitable when two or more inputs may be active simultaneously?

Encoders Hard
A. It automatically selects the lowest-index input
B. It disables its output and floats high-impedance
C. It produces an output that is the OR of the individual codes, which is generally incorrect
D. It outputs all zeros regardless of inputs

54 A 4-bit word is transmitted with an even parity bit . During transmission and both flip. At the receiver, the parity check will:

Parity circuits Hard
A. Pass (no error detected) because two bits flipped
B. Fail, but also correct the error
C. Fail, correctly detecting an error
D. Pass and correct the error

55 A parity generator/checker for a 9-bit code (8 data + 1 parity) is built from a tree of 2-input XOR gates. The minimum number of gate delays (tree depth) to compute the parity of 8 data bits is:

Parity circuits Hard
A.
B.
C.
D.

56 Two logic families are compared: Family X has and ; Family Y has and . Comparing their speed-power products:

Introduction to different logic families Hard
A. Family X is better with
B. Family X is better with
C. Family Y is better with
D. Both have equal speed-power product of

57 For a logic family, , , , . The high-state and low-state noise margins are:

Introduction to different logic families Hard
A. ,
B. ,
C. ,
D. ,

58 In a standard TTL NAND gate, the totem-pole output stage includes a diode between the pull-up transistor's emitter and the pull-down transistor's collector. Its primary purpose is to:

Structure and operations of TTL, MOS and CMOS logic families Hard
A. Reduce the input clamping threshold
B. Increase the output current sinking capability
C. Ensure the upper transistor is off when the output is low, preventing conduction overlap
D. Provide reverse-polarity protection at the input

59 A CMOS inverter driving a capacitive load at switches at . Its dynamic power dissipation is approximately:

Structure and operations of TTL, MOS and CMOS logic families Hard
A.
B.
C.
D.

60 A designer connects an unused input of a CMOS NAND gate by leaving it floating. The most likely consequence is:

Structure and operations of TTL, MOS and CMOS logic families Hard
A. The gate is permanently damaged immediately
B. Erratic output and increased power due to the input drifting near the switching threshold
C. The output is forced to a stable logic low
D. Guaranteed logic-high behavior with no side effects
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