Unit 6: Field Effect Transistors and FET Biasing - Practice Quiz

CSE212 — Electronic Devices And Circuits 60 Questions
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1 What does the acronym JFET stand for?

Construction and Characteristics of JFETs Easy
A. Joint Frequency Emission Transistor
B. Junction Field Effect Transistor
C. Junction Frequency Effect Transistor
D. Joint Field Effect Transistor

2 What are the three terminals of a standard JFET?

Construction and Characteristics of JFETs Easy
A. Anode, Cathode, Gate
B. Input, Output, Ground
C. Base, Emitter, Collector
D. Drain, Source, Gate

3 How does the physical construction of a Depletion-Type MOSFET differ primarily from a JFET?

Depletion-Type MOSFET Easy
A. It is made exclusively of germanium.
B. It has an insulated gate separated by a silicon dioxide layer.
C. It does not have a drain terminal.
D. It has two gates instead of one.

4 What is the state of an Enhancement-Type MOSFET when the gate-to-source voltage () is zero?

Enhancement-Type MOSFET Easy
A. It is fully ON (maximum current).
B. It is normally OFF (zero drain current).
C. It is in the ohmic region.
D. It operates as a constant voltage source.

5 In a Fixed-Bias JFET configuration, what is the ideal value of the DC gate current ()?

Fixed-Bias Configuration Easy
A.
B.
C.
D.

6 In a Self-Bias JFET circuit, how is the required negative gate-to-source voltage () typically developed?

Self-Bias Configuration Easy
A. By shorting the drain to the gate.
B. Across the source resistor () due to the drain current.
C. Through a transformer at the input.
D. By using an external negative battery at the gate.

7 In a Voltage-Divider bias configuration for a FET, what components establish the gate voltage ()?

Voltage-Divider Biasing Easy
A. An inductor connected to the drain.
B. A capacitor connected to the source.
C. Two resistors connected in series across the DC power supply.
D. A single resistor connected to ground.

8 Which parameter on a JFET datasheet indicates the maximum drain current when the gate is shorted to the source ()?

Understanding the datasheets of FET Easy
A.
B.
C.
D.

9 What type of devices are the 2N5457, 2N5458, and 2N5459 commonly classified as in their datasheets?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Easy
A. N-channel JFETs
B. P-channel MOSFETs
C. Enhancement-type MOSFETs
D. NPN Bipolar Junction Transistors

10 Which of the following is a recent trend in semiconductor device design aimed at overcoming the limitations of planar transistors at microscopic scales?

recent trends in electronics Easy
A. Point-contact transistors
B. FinFET (Fin Field Effect Transistor)
C. Vacuum tubes
D. Electromechanical relays

11 What parameter is primarily used to control the current flowing between the drain and source in a JFET?

Construction and Characteristics of JFETs Easy
A. Collector-to-emitter voltage ()
B. Drain resistance ()
C. Gate-to-source voltage ()
D. Base current ()

12 A Depletion-Type MOSFET is unique because it can operate in which two modes?

Depletion-Type MOSFET Easy
A. Active mode and Saturation mode
B. Depletion mode and Enhancement mode
C. Forward mode and Reverse mode
D. Bipolar mode and Unipolar mode

13 In an Enhancement-Type MOSFET, what is the term for the minimum gate-to-source voltage required to form a conducting channel?

Enhancement-Type MOSFET Easy
A. Pinch-off voltage ()
B. Breakdown voltage ()
C. Saturation voltage ()
D. Threshold voltage ( or )

14 Why is a coupling capacitor commonly placed at the input terminal of a FET amplifier circuit?

Fixed-Bias Configuration Easy
A. To increase the power dissipation of the circuit.
B. To amplify the DC voltage.
C. To convert AC signals into DC signals.
D. To block DC signals while allowing AC signals to pass.

15 What is the standard mathematical expression for the gate-to-source voltage () in an N-channel Self-Bias JFET circuit?

Self-Bias Configuration Easy
A.
B.
C.
D.

16 When analyzing a FET voltage-divider bias circuit, the current flowing into the gate terminal is assumed to be:

Voltage-Divider Biasing Easy
A. Infinite
B. Equal to the supply current
C. Equal to the drain current
D. Zero

17 On a JFET datasheet, the parameter represents:

Understanding the datasheets of FET Easy
A. The gate-to-source voltage at which the drain current drops to near zero (pinch-off).
B. The maximum safe operating voltage.
C. The voltage required to break down the gate insulation.
D. The gate-to-source voltage that turns the JFET fully ON.

18 According to typical datasheets for the 2N5457 series JFETs, what is a primary application for these devices?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Easy
A. Microwave frequency rectification
B. Low-level audio and general-purpose amplification
C. High-power AC transmission
D. High-voltage industrial motor control

19 Which wide-bandgap semiconductor material is currently a major trend in high-efficiency, high-frequency power FETs, often replacing standard silicon?

recent trends in electronics Easy
A. Aluminum Oxide
B. Germanium (Ge)
C. Gallium Nitride (GaN)
D. Polystyrene

20 Compared to Bipolar Junction Transistors (BJTs), what is a major advantage of Field Effect Transistors (FETs)?

Construction and Characteristics of JFETs Easy
A. They are controlled by current rather than voltage.
B. They have lower power handling capabilities.
C. They have a significantly higher input impedance.
D. They require higher input currents to operate.

21 In an n-channel JFET, if is made more negative than the pinch-off voltage , what happens to the drain current ?

Construction and Characteristics of JFETs Medium
A. It drops to approximately zero
B. It remains constant at
C. It increases exponentially
D. It becomes dependent on

22 Calculate the drain current for an n-channel JFET given , , and using Shockley's equation.

Construction and Characteristics of JFETs Medium
A.
B.
C.
D.

23 How does a Depletion-Type MOSFET differ from a JFET in terms of its operating regions?

Depletion-Type MOSFET Medium
A. It can only operate in the depletion mode
B. It can operate in both depletion and enhancement modes
C. It operates purely as a voltage-controlled capacitor
D. It cannot reach a pinch-off state

24 For an n-channel D-MOSFET with and , what is when ?

Depletion-Type MOSFET Medium
A.
B.
C.
D.

25 Why is there no drain current in an Enhancement-Type MOSFET when ?

Enhancement-Type MOSFET Medium
A. The substrate is always forward-biased
B. No physical channel exists between the drain and source initially
C. The pinch-off voltage completely blocks the channel
D. The gate terminal is shorted to the source

26 For an n-channel E-MOSFET, if the threshold voltage and the conduction parameter , find when .

Enhancement-Type MOSFET Medium
A.
B.
C.
D.

27 In a JFET fixed-bias configuration, the gate voltage is strictly determined by:

Fixed-Bias Configuration Medium
A. The voltage-divider network at the input
B. The source resistor voltage drop
C. The voltage drop across the drain resistor
D. A dedicated external DC voltage source

28 Consider a JFET fixed-bias circuit with , , and . If the resulting , what is the drain-to-source voltage ?

Fixed-Bias Configuration Medium
A.
B.
C.
D.

29 In a self-bias JFET circuit, how is the negative gate-to-source voltage generated without a separate negative gate supply?

Self-Bias Configuration Medium
A. By the voltage drop across a source resistor due to
B. By using a depletion-mode operation only
C. By the voltage drop across the drain resistor
D. By forward biasing the gate-source junction

30 An n-channel JFET in a self-bias circuit has and a source resistor . What is the value of ?

Self-Bias Configuration Medium
A.
B.
C.
D.

31 When plotting the self-bias DC load line on the JFET transfer characteristics, what two points are most commonly used to draw the line?

Self-Bias Configuration Medium
A. and
B. and
C. and a point defined by
D. and

32 In a JFET voltage-divider bias circuit with , , and , assuming gate current is negligible, what is the gate voltage ?

Voltage-Divider Biasing Medium
A.
B.
C.
D.

33 Which of the following statements is true regarding Voltage-Divider Biasing for an Enhancement-Type MOSFET?

Voltage-Divider Biasing Medium
A. The voltage at the gate must be less than for n-channel devices
B. The gate voltage is established by the divider network, and
C. is determined entirely independent of the drain current
D. The circuit requires two distinct DC power supplies to function

34 If an n-channel JFET with voltage-divider bias has and requires a quiescent , what must be the voltage drop across the source resistor ?

Voltage-Divider Biasing Medium
A.
B.
C.
D.

35 On a JFET datasheet, the parameter (or ) represents the forward transfer admittance. How is this parameter fundamentally related to JFET characteristics?

Understanding the datasheets of FET Medium
A. It indicates the input capacitance of the gate
B. It is the ratio of output voltage to input voltage
C. It is the maximum allowable drain current
D. It represents the change in drain current for a given change in gate-to-source voltage (transconductance)

36 Why do FET datasheets heavily specify the parameter (Gate Reverse Current), and what does a very low value indicate?

Understanding the datasheets of FET Medium
A. It indicates the leakage current of the reverse-biased gate-source junction; a low value confirms high input impedance
B. It represents the breakdown voltage; a low value indicates a fragile device
C. It shows the maximum power dissipation; a low value means high efficiency
D. It is the saturation current; a low value means better amplification

37 The 2N5457, 2N5458, and 2N5459 are commonly grouped together in datasheets. What primary characteristic typically distinguishes these specific JFET models from each other?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Medium
A. Their maximum drain-source voltage ratings
B. The polarity of their channels (n-channel vs p-channel)
C. Their physical package types (TO-92 vs SOT-23)
D. The specified ranges of and pinch-off voltage

38 When looking at a datasheet for the 2N5457 n-channel JFET, the parameter is given as a negative value range. What happens if the applied exceeds the most negative value in this range?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Medium
A. The device enters the ohmic region
B. The transconductance reaches its absolute maximum
C. The drain current drops to zero (cutoff region)
D. The device experiences thermal runaway

39 In modern high-density integrated circuits, which technology has largely succeeded traditional planar MOSFETs to mitigate short-channel effects at nodes below ?

recent trends in electronics Medium
A. Vacuum Tube Micro-Triodes
B. Junction Field-Effect Transistors (JFETs)
C. Bipolar Junction Transistors (BJTs)
D. FinFETs (Fin Field-Effect Transistors)

40 Which semiconductor material is currently a major focus in recent electronics trends for high-power, high-frequency FET devices, largely displacing silicon in specialized RF and power electronics?

recent trends in electronics Medium
A. Aluminum (Al)
B. Indium Phosphide (InP)
C. Germanium (Ge)
D. Gallium Nitride (GaN)

41 In the construction of an n-channel JFET, as the drain-to-source voltage () increases while keeping , the depletion region widens asymmetrically. Which of the following best explains the primary analytical reason for this severe asymmetry prior to pinch-off?

Construction and Characteristics of JFETs Hard
A. The gate-channel junction is uniformly reverse-biased, but electron velocity saturation at the drain end causes charge pooling.
B. The ohmic voltage drop across the channel causes the reverse-bias voltage between the gate and the channel to be highest at the drain end.
C. The intrinsic carrier concentration becomes depleted due to thermal heating localized at the drain terminal.
D. The p-type gate material naturally diffuses deeper into the n-type channel near the drain terminal during fabrication.

42 A specific JFET has and . Using Shockley's equation, determine the transconductance () of the device precisely when the drain current is .

Construction and Characteristics of JFETs Hard
A.
B.
C.
D.

43 An n-channel Depletion-Type MOSFET is characterized by and . If the device is operated in the enhancement mode with a gate-to-source voltage , what is the theoretical drain current assuming Shockley's equation holds strictly in this region?

Depletion-Type MOSFET Hard
A.
B.
C.
D.

44 An n-channel Enhancement-Type MOSFET is biased using a drain-feedback configuration with , , and . The MOSFET parameters are and . Calculate the operating drain current .

Enhancement-Type MOSFET Hard
A.
B.
C.
D.

45 A Fixed-Bias circuit is designed for a JFET. The circuit experiences a temperature increase causing the reverse saturation current of the gate-source junction to rise significantly. How does this non-ideal effect dynamically alter the intended fixed-bias Q-point?

Fixed-Bias Configuration Hard
A. The fixed supply absorbs the leakage current completely, keeping strictly constant and the Q-point completely immovable.
B. The leakage current induces channel length modulation, shifting the pinch-off voltage to a more negative value and decreasing .
C. The increased gate leakage current flows through the external gate resistor , creating a positive voltage drop that makes less negative, thereby increasing .
D. The increased gate leakage current directly subtracts from the drain current, lowering the apparent without affecting .

46 An n-channel JFET with and is used in a self-bias circuit with a source resistor . Assuming the gate is grounded through a resistor, determine the exact steady-state drain current .

Self-Bias Configuration Hard
A.
B.
C.
D.

47 In a JFET self-bias configuration, if the source resistor is allowed to approach infinity (while a proportionally infinite maintains operation), to what theoretical limits do and converge?

Self-Bias Configuration Hard
A. and
B. and
C. and
D. and

48 A voltage-divider biased n-channel JFET circuit has , , , , and . If the JFET parameters are and , calculate the minimum allowable necessary to keep the JFET precisely at the boundary of the saturation (pinch-off) region, assuming the Q-point currents remain unchanged.

Voltage-Divider Biasing Hard
A.
B.
C.
D.

49 In a BJT voltage-divider bias circuit, exact analysis requires calculating the Thévenin resistance to account for base current. When evaluating an identical voltage-divider topology for a JFET bias circuit, which of the following statements rigorously justifies why the 'approximate' method is theoretically exact for finding the DC gate voltage?

Voltage-Divider Biasing Hard
A. The JFET's transconductance perfectly cancels out the source resistance feedback effect.
B. The pinch-off voltage acts as an internal feedback node that nullifies any Thévenin equivalent resistance effects.
C. The JFET gate-source junction is reverse-biased, presenting near-infinite impedance and zero DC gate current.
D. The voltage divider resistors are typically scaled into the megaohm range, making any microampere gate currents mathematically negligible.

50 On a JFET datasheet, the parameter represents the reverse transfer capacitance. In high-frequency amplifier analysis, how does a larger profoundly degrade circuit performance?

Understanding the datasheets of FET Hard
A. It decreases the output impedance of the JFET, thereby reducing the low-frequency voltage gain.
B. It acts in parallel with the source bypass capacitor, severely shifting the lower cutoff frequency.
C. It directly increases the gate leakage current () during dynamic signal swings, causing thermal runaway.
D. It is multiplied by the voltage gain due to the Miller effect, resulting in a large equivalent input capacitance that lowers the high-frequency cutoff.

51 A FET datasheet provides the small-signal parameters (forward transfer admittance) and (output admittance). Determine the intrinsic theoretical maximum voltage gain (amplification factor ) of this device.

Understanding the datasheets of FET Hard
A.
B.
C.
D.

52 A datasheet for a power MOSFET indicates a maximum power dissipation at a case temperature , with a linear derating factor of . What is the absolute maximum allowable power dissipation if the device is operated at a case temperature of ?

Understanding the datasheets of FET Hard
A.
B.
C.
D.

53 When examining the datasheets for the 2N5457, 2N5458, and 2N5459 series, all three are fundamentally built on the same silicon die architecture but separated into different part numbers. What is the primary basis for sorting these devices into these three specific designations?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Hard
A. Differing maximum breakdown voltages ()
B. Sorting based on tested ranges of and bands
C. Different packaging materials (plastic vs. metal can) altering their thermal resistance
D. Differing internal channel lengths resulting in completely different transconductance limits

54 A designer wants to replace a 2N5457 in a highly stabilized constant-current source circuit with a 2N5459 without changing any resistor values. Based on their respective datasheets, what is the most likely consequence for the circuit's Q-point?

Understanding the datasheet of FETs 2N5457, 2N5458, 2N5459 Hard
A. The drain current will decrease significantly because the 2N5459 has a lower transconductance.
B. The operating point will remain entirely unaffected because self-bias perfectly negates parameter variations.
C. The threshold voltage shifts to a positive value, turning the 2N5459 into an enhancement-mode device.
D. The device will likely enter the ohmic region sooner due to the higher intrinsic of the 2N5459 demanding a larger source bias voltage.

55 In contemporary VLSI scaling, planar MOSFETs have largely been superseded by FinFETs at nodes below 22nm. What fundamental physics limitation of planar MOSFETs is primarily mitigated by the FinFET's 3D architecture?

recent trends in electronics Hard
A. Electromigration in the copper interconnects due to increased current densities
B. Gate oxide tunneling currents caused by excessively thick dielectric materials
C. Drain-Induced Barrier Lowering (DIBL) and related short-channel effects
D. Inadequate charge carrier mobility caused by high substrate doping concentrations

56 The integration of High- dielectrics (e.g., Hafnium Oxide) replaced traditional Silicon Dioxide () in modern MOSFET gate stacks. Which of the following best describes the quantum mechanical and electrostatic necessity for this shift?

recent trends in electronics Hard
A. It prevented the absorption of alpha particles, mitigating soft errors in modern high-density static RAM arrays.
B. It decreased the dielectric constant to reduce the Miller capacitance, dramatically enhancing ultra-high-frequency switching speeds.
C. It allowed for a thicker physical oxide layer to suppress direct quantum tunneling of electrons while maintaining or increasing the equivalent oxide capacitance.
D. It physically altered the bandgap of the silicon channel, converting it from an indirect to a direct bandgap semiconductor for photonic coupling.

57 Gate-All-Around (GAA) or Nanosheet FETs represent the next evolutionary step past FinFETs for the 3nm and 2nm process nodes. What distinct structural advantage does a GAA-FET provide over a standard FinFET?

recent trends in electronics Hard
A. It eliminates the source and drain diffusion regions, relying entirely on Schottky barriers for current injection.
B. It implements a back-gate terminal to dynamically adjust the threshold voltage during active operation.
C. It utilizes vertically stacked horizontal nanosheets where the gate fully surrounds the channel 360 degrees, maximizing electrostatic control per unit footprint.
D. It replaces the semiconductor channel with a single-walled carbon nanotube to bypass velocity saturation limits.

58 Negative Capacitance FETs (NC-FETs) are heavily researched to overcome the fundamental thermionic limit of conventional MOSFETs. What specific performance metric does the NC-FET aim to push below its room-temperature physical limit of ?

recent trends in electronics Hard
A. Drain-to-source on-resistance ()
B. Transconductance efficiency ()
C. Subthreshold swing (SS)
D. The threshold voltage () temperature coefficient

59 In a physical Enhancement-Type MOSFET, the output characteristics display a slight upward slope in the saturation region rather than being perfectly horizontal. This phenomenon is analytically modeled by the parameter . What is the underlying physical cause of this behavior?

Enhancement-Type MOSFET Hard
A. The onset of weak inversion occurring simultaneously with strong inversion at high drain voltages.
B. Avalanche multiplication of carriers near the strongly biased drain junction.
C. Thermal self-heating which reduces electron mobility and increases local conductivity.
D. Channel Length Modulation, where the effective channel length shortens as increases beyond .

60 Consider an Enhancement-Type MOSFET biased deep into the linear (triode) region where is extremely small (). How does the transconductance fundamentally relate to the applied voltages in this specific region of operation?

Enhancement-Type MOSFET Hard
A. is identically zero because the device acts solely as a passive resistor.
B. is inversely proportional to and independent of .
C. is directly proportional to and is largely independent of .
D. exhibits a square-law dependence on .