Unit 6 - Practice Quiz

Nvidia is a leading company in the design and manufacturing of Graphics Processing Units (GPUs), which are crucial for gaming, professional visualization, and high-performance computing.

CUDA (Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) model created by Nvidia that enables developers to harness the power of Nvidia GPUs for tasks beyond graphics rendering.

Supercomputers are designed for high-performance computing (HPC) to solve complex problems in science, engineering, and data analysis that are too large or time-consuming for standard computers.

FLOPS is a standard measure of computer performance, particularly for scientific calculations that use floating-point numbers. Supercomputer performance is often measured in PetaFLOPS (quadrillions of FLOPS) or ExaFLOPS (quintillions of FLOPS).

A qubit, or quantum bit, is the fundamental unit of quantum information, analogous to the classical bit. Unlike a classical bit, it can exist in a superposition of states.

Superposition is a fundamental principle of quantum mechanics that allows a qubit to represent a combination of both 0 and 1 at the same time, which is a key source of a quantum computer's power.

Multi-core architecture involves integrating two or more independent processing units (called 'cores') into a single chip to improve performance, reduce power consumption, and enable more efficient parallel processing.

Microarchitecture, also known as computer organization, is the way a given Instruction Set Architecture (ISA) is implemented in a particular processor. It describes the internal design and data paths of the CPU.

Qualcomm is the developer of the Snapdragon line of System on a Chip (SoC) products, which are widely used in a vast majority of Android-based smartphones and tablets.

A System on a Chip (SoC) is an integrated circuit that combines many or all components of a computer into a single chip. This is common in mobile devices for greater power efficiency and to save space.

Pipelining is a technique where multiple instructions are overlapped in execution. The computer pipeline is divided into stages, and each stage completes a part of an instruction in parallel, increasing the number of instructions executed per unit of time.

Domain-Specific Architecture refers to designing computer architectures that are specialized for a particular application domain (e.g., Google's TPU for machine learning) to achieve higher performance and efficiency than general-purpose CPUs.

Apple transitioned its Mac computers from Intel's x86-64 architecture to its own custom-designed chips based on the ARM architecture, which is known for its high performance per watt (power efficiency).

Supercomputers use massively parallel processing, where a complex problem is broken down into smaller pieces that are solved simultaneously ('in parallel') by thousands or even millions of processor cores.

Quantum entanglement is a phenomenon where the state of one qubit is directly related to the state of another, no matter the distance between them. This property is a key resource in quantum computing algorithms.

The parallel architecture of GPUs is extremely well-suited for the massive matrix and vector operations required in training deep learning models, making them a cornerstone of modern AI and high-performance computing.

A chiplet-based design breaks a large, complex processor into smaller, more manageable chiplets. These can be manufactured separately and then assembled, improving manufacturing yield and allowing for more flexible and scalable designs.

A CPU cache is a small, very fast memory that stores copies of data from main memory (RAM). Since the cache is much faster than RAM, this reduces the average time to access data, thereby improving overall system performance.

RISC stands for Reduced Instruction Set Computer. It is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer cycles per instruction.

Most desktop and server processors from companies like Intel and AMD use the x86 (or x86-64) architecture, which is designed for high performance. Smartphones and other mobile devices prioritize power efficiency and therefore primarily use processors based on the ARM architecture.

Nvidia's Tensor Cores are a key architectural innovation designed to accelerate deep learning training and inference. Their specific function is to perform fused matrix-multiply-accumulate (MMA) operations, which are the computational backbone of neural networks. A CUDA core is a more general-purpose programmable processor for a wider range of parallel tasks, but it is far less efficient at MMA operations than a dedicated Tensor Core.

While high bandwidth is important, applications with frequent, small data exchanges (like many HPC simulations involving Message Passing Interface or MPI) are often limited by latency. Latency is the time it takes for a single message to travel from source to destination. For many small messages, the cumulative delay from latency can dominate the total communication time, creating a performance bottleneck. Technologies like InfiniBand are favored in HPC for their extremely low latency compared to standard Ethernet.

This question tests the understanding of quantum entanglement. Entanglement means the states of the qubits are linked in a way that is not possible classically. Measuring one entangled qubit instantly influences the state of the others, no matter the distance between them. The exact outcome for the other qubits depends on the specific entangled state they were in, but their state is no longer an unconstrained superposition; it is now determined by the measurement of the first qubit.

As processors become more complex, creating a single, large, flawless monolithic die becomes increasingly difficult and expensive, leading to poor manufacturing yields. The chiplet approach breaks the processor into smaller, independent dies (chiplets) which are easier to manufacture with higher yields. These chiplets are then connected on a single package. This also provides the flexibility to use the most advanced process node for critical components like CPU cores, while using a more mature, cost-effective node for less critical components like I/O controllers.

Breaking down instruction execution into more, smaller pipeline stages allows each stage to be simpler and faster, enabling a higher clock frequency for the processor. This increases the theoretical peak instruction throughput (Instructions Per Cycle * Clock Rate). However, the downside is that it takes more clock cycles for a single instruction to complete (higher latency), and if a branch is mispredicted, the entire pipeline must be flushed, and the penalty (lost cycles) is proportional to the depth of the pipeline. Deeper pipelines have a much more severe penalty for mispredictions.

The most significant advantage of RISC-V is its open and extensible model. Unlike ARM and x86 which require expensive licenses, RISC-V is royalty-free. More importantly, its modular design features a small, mandatory base integer ISA with numerous optional standard extensions. Companies can implement the extensions they need and even add their own custom, proprietary extensions to create highly specialized processors for specific workloads (e.g., AI/ML acceleration) without needing permission or paying royalties.

Mobile SoCs are paragons of heterogeneous computing. Instead of relying solely on powerful general-purpose CPU cores, they integrate a suite of specialized hardware accelerators (DSAs - Domain-Specific Architectures) for common tasks like machine learning (NPU), image processing (ISP), and graphics (GPU). These accelerators perform their specific tasks much more efficiently (performance-per-watt) than a CPU would, allowing the SoC to achieve high performance in these areas while staying within a strict thermal and power envelope.

The SIMT model is central to the efficiency of Nvidia GPUs. The SM's instruction dispatcher issues one instruction per cycle to a warp scheduler, which then broadcasts that instruction to all 32 threads in the warp. Each thread executes this same instruction, but on its own private data. This amortizes the cost of instruction fetch and decode across 32 threads, leading to very high arithmetic intensity. If threads in a warp diverge (e.g., due to an if-else statement), the hardware must serialize the execution paths, leading to a performance penalty known as 'warp divergence'.

Amdahl's Law assumes a fixed problem size, meaning the serial portion becomes a larger and larger bottleneck as processors are added. Gustafson's Law takes a different perspective, more relevant to large-scale scientific computing: it assumes that as you get more processors, you'll want to solve a bigger problem. It fixes the execution time and lets the problem size grow. In this model (scaled speedup), the serial portion becomes a smaller and smaller fraction of the total work, leading to a more linear and optimistic scalability prediction.

Decoherence is the process by which a quantum system loses its quantum behavior due to interactions with the external environment (e.g., thermal fluctuations, electromagnetic fields). This interaction essentially 'measures' the qubit, causing its delicate superposition to collapse into a definite classical state. A major part of quantum computer architecture is therefore focused on isolating the qubits from the environment through physical means like extreme refrigeration and magnetic shielding, as well as implementing quantum error correction codes to mitigate its effects.

The Reservation Station is a key component for enabling out-of-order execution. After an instruction is fetched and decoded, it is sent to a reservation station. Here, it monitors the results bus for its required operands. Once all its operands are ready and a suitable functional unit (like an ALU or FPU) is available, the instruction can be dispatched for execution, even if earlier instructions in the program order are still stalled waiting for their own operands. The Reorder Buffer (ROB) is then used to ensure the results are written back in the correct program order.

The slowing of Moore's Law and Dennard scaling has made it difficult to get performance gains from general-purpose CPUs. DSAs offer a solution by creating highly specialized hardware. For example, a TPU is designed with a massive matrix multiplication unit (a systolic array) because that is the dominant operation in neural networks. By stripping away hardware for general-purpose tasks and optimizing for one specific domain, DSAs can achieve much higher performance-per-watt than a CPU or even a GPU on that particular task.

The big.LITTLE architecture is designed for power efficiency, especially in mobile devices. The 'LITTLE' cores are simple, in-order cores optimized for low power consumption and are used for background tasks or light workloads. The 'big' cores are complex, out-of-order cores designed for maximum performance. The operating system scheduler can seamlessly migrate a task from a LITTLE core to a big core when high performance is needed (e.g., launching an app) and back down to a LITTLE core when the task is idle, thus optimizing for the best performance-per-watt across a range of use cases.

The term System-on-Chip (SoC) accurately describes the mobile processor design philosophy: integrating nearly all components of a computer system onto a single piece of silicon. This tight integration is crucial for power efficiency and a small physical footprint. In contrast, while modern desktop CPUs are highly integrated, their focus is on maximizing CPU performance. They typically rely on a separate motherboard chipset for many I/O functions and a discrete GPU for high-end graphics, and are increasingly using chiplets to scale up core counts.

The Hadamard gate (H) is a fundamental quantum gate that transforms a basis state into an equal superposition of its two basis states. Applying H to yields , and applying it to yields . To create a uniform superposition of all states in an n-qubit register initialized to , one must apply a Hadamard gate to each of the n qubits individually.

SMT (like Intel's Hyper-Threading) aims to improve the utilization of a single core's execution resources. The core's microarchitecture is modified to have multiple sets of architectural state registers. This allows the core to fetch and decode instructions from multiple threads simultaneously. When one thread stalls (e.g., due to a cache miss), instructions from another active thread can be issued to the shared execution units (ALUs, FPUs, etc.), hiding the latency and keeping the pipeline busy, thus increasing overall throughput.

Transformer models, which are foundational to large language models like GPT, are computationally intensive. The Transformer Engine in the Hopper architecture is a hardware and software system that uses mixed-precision arithmetic to accelerate these models. It can intelligently and dynamically switch between lower-precision 8-bit floating point (FP8) for matrix multiplications and higher-precision 16-bit floating point (FP16) for accumulations and other sensitive parts of the calculation, dramatically increasing throughput and reducing memory footprint while maintaining the model's accuracy.

HPC applications often have massive I/O requirements, such as checkpointing a large simulation or reading in huge datasets. A traditional file system (like NFS) would become a severe bottleneck. Parallel file systems solve this by striping data across many independent storage servers and disks. This architecture allows many clients (the compute nodes) to read and write different parts of a single logical file in parallel, providing the massive aggregate I/O bandwidth needed to keep the compute resources fed with data.

In a von Neumann architecture, execution is control-flow driven, dictated by a program counter that steps through instructions in sequence. In a pure dataflow architecture, there is no program counter. Instead, execution is data-driven. An instruction (or node in a dataflow graph) becomes 'fireable' or ready for execution only when all of its input operands have arrived. This model exposes a high degree of parallelism naturally and is influential in the design of some specialized accelerators.

In traditional architectures, data must be constantly shuttled between the main memory (DRAM) and the CPU for processing. This data movement consumes a significant amount of time and energy, a problem known as the Memory Wall or von Neumann bottleneck. PIM/CIM architectures try to solve this by integrating computational logic directly within or near the memory arrays. This allows simple computations (e.g., addition, multiplication, bitwise operations) to be performed on the data in place, drastically reducing data movement and improving energy efficiency for data-intensive applications.

The key innovation of the Transformer Engine in the H100 GPU is its ability to dynamically manage precision. It analyzes the statistics of the neural network layers and automatically casts data to FP8 for computation where possible, and back to FP16 for accumulation to preserve accuracy. This dynamic, fine-grained precision switching is the core mechanism that boosts performance significantly on transformer models. Option B is incorrect; while FP8 is used, it's not exclusive, and FP4 is not the standard format introduced. Option C is an overstatement; warp scheduling is still fundamental. Option D confuses the role of Tensor Cores with interconnect technology.

Tiling is the canonical optimization for stencil computations. By loading a tile into shared memory, each element is fetched from slow global memory only once. The 8 neighbor accesses for threads within the tile can then be satisfied by the fast, on-chip shared memory, drastically reducing global memory traffic and latency. Option B helps but doesn't solve the fundamental problem of redundant global memory fetches for neighboring data. Option C might hide some latency but doesn't reduce the memory bandwidth pressure, which is the root cause. Option D addresses host-to-device transfer latency, not the in-kernel global memory access latency, which is the bottleneck described.

The Dragonfly topology is hierarchical, with high-bandwidth local links within a group and a smaller number of global links connecting groups. In an all-to-all communication pattern, every node communicates with every other node, placing immense and uniform pressure on the limited global links. This can lead to significant contention and network congestion, becoming the primary bottleneck. Adaptive routing is crucial to try and spread the load over available paths. Option B is incorrect; Dragonfly is designed to have a low diameter. Option C is a physical layer detail and not the primary topological challenge. Option D is incorrect; modern Dragonfly implementations rely heavily on adaptive routing.

The state can be factored using tensor product algebra: . Since the state can be written as a tensor product of two single-qubit states (proportional to and ), it is a product state, and the qubits are not entangled. Option B is incorrect; Bell states are the canonical examples of entangled states. Option C describes an invalid collapse; the second qubit would collapse to the valid state . Option D is incorrect; applying H ⊗ H to the factored state gives (H) ⊗ (H) = |0⟩ ⊗ |1⟩ = |01⟩.

1. P1 reads X: This is a cache miss. P1 issues a BusRd to memory. Since no other cache has the block, P1 loads it in the Exclusive (E) state. (Total: 1 BusRd).
2. P2 writes to X: This is a write miss. P2 issues a BusRdX (Read for Ownership) to get the data and invalidate other copies. P1's snooper sees the BusRdX, invalidates its copy (E -> I), and P2 loads the data in the Modified (M) state. (Total: 1 BusRd, 1 BusRdX).
3. P1 reads X: This is a cache miss (its copy is Invalid). P1 issues a BusRd. P2's snooper sees the BusRd, provides the data from its M-state block, and transitions its own block from M -> Shared (S). P1 loads the data in the S state. (Total: 2 BusRd, 1 BusRdX).
   This sequence results in exactly two BusRd transactions and one BusRdX transaction.

The primary challenge in a UMA system is managing the shared memory resource. The CPU requires low-latency access for its operations to avoid stalling. The GPU, being a throughput-oriented processor, issues massive, parallel requests that demand high bandwidth. A sophisticated memory controller with complex QoS logic is essential to prioritize CPU requests to maintain system responsiveness while still feeding the GPU enough data to prevent it from being starved. This arbitration is a major design challenge. Option B is a trade-off, but modern LPDDR5X offers very high bandwidth. Option C is incorrect; the address space is typically large (64-bit). Option D is a factor, but modern SoCs have highly optimized coherence fabrics to handle this efficiently, making contention (Option A) the more dominant architectural challenge.

CXL.mem uses a 'Host-managed Device Memory' model. The host CPU's coherence protocol is extended to manage the CXL memory. When the host caches a line from the CXL device, the CXL memory controller acts as the 'home agent' for that address. It maintains a directory to track the state of that cache line within the host's caches. If the host needs to write, it sends requests to the CXL controller, which then sends invalidations to other sharers if necessary. This allows the host to cache CXL memory coherently without the device itself needing a complex snooping mechanism. Option B would be extremely inefficient. Option C is not scalable for the point-to-point CXL topology. Option D defeats the purpose of hardware cache coherence provided by CXL.mem.

The core trade-off is performance versus cost/power. A high-bandwidth, low-latency link is desired, but this costs power and requires complex physical-layer design. Crucially, no matter how fast the link is, accessing data on another chiplet will be slower than accessing local resources. This creates a NUMA effect within the CPU package itself. Optimizing the fabric involves a delicate balance: making it fast enough to minimize this NUMA penalty for most workloads, but not so power-hungry that it negates the efficiency gains of the chiplet design. The other options are less central to the core architectural performance trade-off.

The fundamental driver for CPU+GPU heterogeneity in HPC is energy efficiency, measured in FLOPS/watt. A CPU is designed for low latency on complex tasks, which requires power-hungry control logic and large caches. A GPU is designed for massive throughput on simple, parallel tasks, dedicating more silicon to execution units. This results in a much higher number of floating-point operations per watt for suitable workloads. By offloading the parallel computation to the more efficient GPUs, the overall system can achieve a much higher total FLOPS for a given power budget. The other options are secondary effects or incorrect.

Classical TMR works by making three identical copies of a bit and using a majority vote. The No-Cloning Theorem states that it is impossible to create an identical copy of an arbitrary, unknown quantum state. Therefore, this simple redundancy is impossible for qubits. Quantum Error Correction (QEC) codes circumvent this by using entanglement. They encode the state of a single logical qubit into an entangled state of multiple physical qubits. Errors can be detected by measuring an 'error syndrome' without measuring and collapsing the logical qubit's state. The information is distributed, not copied. Option B is partially true but not the root cause. C is a technique used in QEC but not the fundamental reason. D is incorrect; the goal of QEC is to correct the state.

NVIDIA's structured sparsity requires a specific 2:4 pattern: in each contiguous block of 4 weights, at least 2 must be zero. The hardware identifies this structure, loads only the non-zero weights and their indices, and performs the computation at twice the rate. The major constraint is that this pattern is not natural; networks must be trained with specific pruning techniques to achieve this structure while maintaining accuracy. Option B describes unstructured sparsity, which is harder to accelerate. Option C describes a different approach. Option D is incorrect; sparsity is supported for FP16, BF16, and INT8.

When the load instruction stalls, it is placed in a Reservation Station awaiting its data. The Reorder Buffer (ROB) tracks the original program order. The processor can continue to dispatch subsequent, independent instructions to other Reservation Stations for execution. The ROB ensures that instructions commit in the original program order, preserving program semantics and enabling precise exceptions. The components in A are the core structures that manage the out-of-order window. B relates to the front-end, C is specific to memory ordering, and D lists execution units, which are used by independent instructions but do not manage the overall out-of-order process.

While B, C, and D are all significant challenges, cache coherence is the most complex architectural problem. When PIM logic modifies data in memory, any copies of that data in the CPU's multi-level cache hierarchy become stale. A robust and efficient coherence mechanism is required to either invalidate or update the CPU caches. Standard protocols are difficult to implement across the memory bus to potentially thousands of PIM units. Without a hardware solution, the system must resort to slow, software-managed cache flushes, which would negate much of the performance benefit of PIM.

This scenario illustrates the intended use of a hybrid architecture. The main application thread and user-facing threads are latency-sensitive and benefit from the high single-threaded performance of the P-cores. The encoding task contains many sub-tasks that are highly parallel but less sensitive to the latency of any single one. These are ideal for the E-cores, which provide excellent multi-threaded throughput within a small power and area budget. This division of labor maximizes both performance and efficiency. B would sacrifice performance. C would be inefficient due to migration overhead. D is a possible thermal strategy, but it's not the primary, most effective scheduling policy for this workload.

The defining characteristic of a systolic array is its data flow pattern. Weights are pre-loaded into the processing elements, and activations are 'pumped' through the array. Each piece of data loaded from memory is used in multiple computations as it passes through the PEs. This massive data reuse is the key to its efficiency. In a conventional architecture, data is repeatedly read from a large register file or shared memory for each MAC operation, and data movement is far more energy-expensive than the computation itself. While B, C, and D are contributing factors, the fundamental architectural principle is the extreme data reuse described in A.

This is a key trade-off in quantum hardware. While trapped ions boast very long coherence times (seconds), their gate operations are slow (microseconds). Superconducting transmons have much shorter coherence times (microseconds), but their gates are orders of magnitude faster (nanoseconds). The relevant figure of merit is the number of high-fidelity operations one can perform within the coherence time. The faster gate speeds of transmons often allow for more complex algorithms to be run before the state decoheres, leading to a higher 'Quantum Volume' or better computational capability for near-term devices. While B and C are also important advantages, A is the most critical reason for their computational power in the NISQ era.

The power of a global history predictor comes from its ability to recognize patterns based on the path taken to reach a branch. In scenario A, the behavior of the inner if (y > 10) branch might be strongly correlated with whether the outer if (x > 0) branch was taken. The GHR captures this path information. A simple Bimodal predictor, which only looks at the address of the inner branch, would see a mixed history and predict poorly. The GAg predictor can learn that 'when the global history reflects the outer branch was taken, this inner branch is likely not taken,' and vice versa. B and D describe simple patterns that a bimodal predictor's saturating counters can learn effectively. C is the worst-case for any predictor.

The main criticism of HPL is its 'perfect' workload characteristics. Solving a dense matrix problem involves predictable, streaming memory accesses and a very high number of calculations for every byte of data moved. This allows systems to achieve near-peak FLOPS because compute units are constantly fed with data from caches and prefetchers. However, many real-world applications (e.g., climate modeling, bioinformatics) involve irregular, pointer-chasing memory accesses that result in poor cache utilization and are often bottlenecked by memory latency and interconnect performance, not raw FLOPS. A machine excelling at HPL may not perform as well on these other important workloads. B is a valid point, but A is the more fundamental architectural criticism. C is incorrect; HPL is highly parallelizable. D is incorrect; HPL is compute-bound.

Constant memory is specifically designed for this use case. When all threads in a warp access the same address in constant memory (as they would when reading the same filter coefficient), the request is serviced from the dedicated constant cache and the value is broadcast to all threads in a single transaction. This is extremely efficient. While shared memory (B) is fast, it would require each block to explicitly load the filter into its limited shared memory. Using __ldg() (C) is a good general strategy for caching global memory, but constant memory's broadcast mechanism is superior for this specific uniform-access pattern. Pinned memory (D) optimizes host-device transfers, not in-kernel access.

The primary benefit of a massive L3 cache is to drastically improve the hit rate, reducing the number of times the CPU must go to main DRAM. Accessing DRAM is a very high-latency operation (hundreds of CPU cycles). Applications like gaming often have large working sets and access patterns that are not always predictable, leading to L3 misses. By making the L3 cache large enough to hold a significant portion of the application's working set, the 3D V-Cache architecture turns many would-be DRAM accesses into much faster L3 cache hits. This reduction in average memory access latency is the key performance benefit. B is a secondary benefit. C is not the primary goal. D is incorrect; the technology is used to expand the L3 cache, not the L2 caches.