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Unit 6 - Practice Quiz

CSE211

1 In the context of Nvidia GPU architecture, what does the acronym SIMT stand for?

A. Single Instruction, Multiple Threads
B. Single Instruction, Multiple Tasks
C. Simultaneous Instruction, Memory Transfer
D. Single Integer, Multiple Tensors

2 In an Nvidia CUDA architecture, a collection of threads that execute the same instruction together is technically referred to as a:

A. Grid
B. Block
C. Warp
D. Cluster

3 Which of the following memory types in a GPU hierarchy usually has the lowest latency?

A. Global Memory
B. Texture Memory
C. Local Memory (off-chip)
D. Shared Memory / L1 Cache

4 What is the primary function of Tensor Cores introduced in Nvidia's Volta and subsequent architectures?

A. Accelerating ray tracing calculations
B. Managing video output to monitors
C. Accelerating matrix-multiply-and-accumulate operations for AI
D. Handling standard integer arithmetic

5 When threads in a warp follow different execution paths due to a conditional branch (e.g., if-else), this phenomenon is known as:

A. Thread Convergence
B. Thread Divergence
C. Warp Serialization
D. Deadlock

6 In the CUDA programming model, what is the hierarchy of thread organization from largest to smallest?

A. Grid Block Thread
B. Block Grid Thread
C. Thread Warp Grid
D. Cluster Grid Block

7 Which benchmark is predominantly used to rank the world's fastest supercomputers in the TOP500 list?

A. Geekbench
B. SPEC CPU
C. Linpack (HPL)
D. Cinebench

8 The performance of supercomputers is most commonly measured in:

A. MIPS (Million Instructions Per Second)
B. FLOPS (Floating Point Operations Per Second)
C. RPM (Rotations Per Minute)
D. IOPS (Input/Output Operations Per Second)

9 An Exascale supercomputer is capable of calculating at least how many operations per second?

A. (1 TeraFLOPS)
B. (1 PetaFLOPS)
C. (1 ExaFLOPS)
D. (1 ZettaFLOPS)

10 In quantum computing, what is the fundamental unit of information?

A. Transistor
B. Qubit
C. Byte
D. Neuron

11 Which quantum phenomenon allows a Qubit to exist in a state that is a combination of both |0 and |1 simultaneously?

A. Entanglement
B. Superposition
C. Tunneling
D. Decoherence

12 Mathematically, a Qubit state is represented as . What must be true about and ?

A.
B.
C.
D.

13 What is Quantum Entanglement?

A. The error rate caused by heat in a quantum processor
B. A state where two qubits operate independently
C. A phenomenon where the state of one qubit is instantly correlated with another, regardless of distance
D. The process of converting a qubit to a classical bit

14 What is the major challenge in building stable quantum computers that involves the loss of quantum information to the environment?

A. Superposition
B. Decoherence
C. Compilation
D. Latency

15 Which of the following is a trend in modern computer architecture to overcome the 'Power Wall'?

A. Increasing clock frequency to 10GHz+
B. Moving from multi-core to single-core designs
C. Heterogeneous computing (Specialized accelerators like NPUs/TPUs)
D. Removing cache memory

16 What is a Chiplet design in next-generation processor architecture?

A. A single monolithic die containing all components
B. A software simulator for chips
C. Breaking a large processor into smaller modular dies connected via a high-speed interconnect
D. A chip designed only for smartphones

17 What does Moore's Law state?

A. Processor speed doubles every 6 months
B. The number of transistors on a microchip doubles about every two years
C. Power consumption halves every year
D. Memory latency decreases by 50% every two years

18 Which architecture feature is used in modern CPUs to execute instructions out of their original program order to utilize idle execution units?

A. In-order Execution
B. Out-of-Order Execution
C. Static Scheduling
D. Blocking I/O

19 What is the purpose of Branch Prediction in microarchitecture?

A. To guess the outcome of a conditional operation to keep the pipeline full
B. To predict when the computer will crash
C. To route data to the correct memory bank
D. To increase the clock speed of the RAM

20 What is Dark Silicon?

A. Silicon that is painted black for heat dissipation
B. Defective parts of a wafer
C. The portion of a chip that must be powered off at any given time to prevent overheating
D. Silicon used only for cache memory

21 Which instruction set architecture (ISA) is open-source and rapidly gaining popularity in next-gen embedded and computing applications?

A. x86
B. ARM
C. RISC-V
D. MIPS

22 The big.LITTLE (or hybrid) architecture found in modern smartphone processors involves:

A. Mixing vacuum tubes with transistors
B. Combining high-performance cores with power-efficient cores
C. Using a big screen with a little battery
D. Combining a GPU and a sound card only

23 Apple's M-series chips utilize a Unified Memory Architecture (UMA). What is the main benefit of this?

A. It allows the CPU and GPU to access the same data without copying it over a bus
B. It increases the total storage capacity of the hard drive
C. It separates video memory from system memory completely
D. It allows the user to upgrade RAM easily

24 What is an SoC (System on Chip)?

A. A chip that only handles system operating system tasks
B. An integrated circuit that integrates all components of a computer (CPU, Memory, GPU, I/O) on a single substrate
C. A separate chip used for cooling the system
D. A standard for connecting peripherals

25 Which component in a modern smartphone processor is dedicated to processing AI and Machine Learning tasks?

A. ALU (Arithmetic Logic Unit)
B. NPU (Neural Processing Unit)
C. MMU (Memory Management Unit)
D. NIC (Network Interface Card)

26 In GPU architecture, what does GPGPU stand for?

A. General-Purpose computing on Graphics Processing Units
B. Graphical Processing for Games and Processing Units
C. Global Position GPU
D. Gigabyte Processing Graphics Unit

27 Which of the following best describes 3D V-Cache or 3D Stacking technology?

A. Viewing the cache through 3D glasses
B. Stacking memory layers vertically on top of the processor die to increase cache size and bandwidth
C. Arranging three processors in a triangle
D. Using 3D printing to create chips

28 The Top500 list is updated how frequently?

A. Once a year
B. Twice a year (June and November)
C. Every month
D. Every 5 years

29 In the context of Supercomputers, what is a Cluster?

A. A single giant processor
B. A group of linked computers working together closely so they resemble a single computer
C. A defect in the hard drive
D. A type of cooling fluid

30 Which interconnect technology is commonly used in supercomputers for low latency and high bandwidth?

A. USB 2.0
B. InfiniBand
C. Bluetooth
D. Wi-Fi 6

31 What is Quantum Supremacy (or Quantum Advantage)?

A. When a quantum computer becomes self-aware
B. The point where a quantum computer can solve a problem that is practically impossible for a classical supercomputer
C. When quantum computers replace all classical computers
D. The ability to teleport matter

32 In microarchitecture, Superscalar means:

A. The processor is very large
B. The processor executes more than one instruction per clock cycle
C. The processor uses scalar data only
D. The clock speed is over 5GHz

33 What is the primary difference between RISC (e.g., ARM) and CISC (e.g., x86) architectures?

A. RISC has complex instructions taking multiple cycles; CISC has simple instructions
B. RISC relies on simple, single-cycle instructions; CISC has complex instructions performing multiple operations
C. RISC is only for desktops; CISC is only for mobiles
D. There is no difference

34 What is Speculative Execution?

A. Executing code only after verifying it is correct
B. Executing instructions before it is known if they are needed, to prevent delays
C. Guessing the password of a user
D. Running a virus scan

35 Which physical constraint refers to the inability to scale down voltage further as transistors shrink, leading to higher power density?

A. Dennard Scaling Breakdown
B. Amdahl's Law
C. Gustafson's Law
D. Newton's Third Law

36 Modern desktop processors often use SMT. What does it stand for?

A. System Memory Translation
B. Simultaneous Multi-Threading
C. Static Media Transport
D. Single Mode Transfer

37 Which company designs the Snapdragon series of SoCs found in many Android smartphones?

A. Nvidia
B. Qualcomm
C. Intel
D. AMD

38 The Hadamard Gate in quantum computing is used to:

A. Create a superposition state from a basis state
B. Copy a qubit
C. Delete a qubit
D. Measure a qubit

39 What is HBM (High Bandwidth Memory), often used with high-end GPUs?

A. A type of hard drive
B. Stacked memory chips connected via Through-Silicon Vias (TSV) for wide data paths
C. Memory that runs at 10GHz
D. A USB stick format

40 In the context of the Nvidia Case Study, what is the Grid?

A. The power supply unit
B. The layout of the PCB
C. The highest level of the thread hierarchy, containing all blocks for a kernel launch
D. The cooling fan array

41 What is the typical size of a Warp in current Nvidia GPUs?

A. 8 threads
B. 16 threads
C. 32 threads
D. 64 threads

42 Which law suggests that the speedup of a program from parallelization is limited by the sequential portion of the program?

A. Moore's Law
B. Amdahl's Law
C. Faraday's Law
D. Murphy's Law

43 In modern manufacturing (e.g., 5nm, 3nm), what does the nanometer number primarily represent in marketing terms?

A. The actual gate length of the transistor
B. The size of the entire chip
C. A process node generation label indicating density and efficiency improvements
D. The distance between the CPU and RAM

44 What is the role of the Scheduler in a GPU Streaming Multiprocessor (SM)?

A. To schedule meetings for the developers
B. To select which warps are ready to execute and dispatch instructions to execution units
C. To manage the fan speed
D. To convert AC power to DC

45 Which of the following is a characteristic of Domain Specific Architectures (DSA)?

A. They are general-purpose and perform reasonably well at everything
B. They are tailored to a specific class of problems (e.g., deep learning) to achieve high efficiency
C. They use the x86 instruction set only
D. They consume more power than general CPUs

46 What is ROB (Reorder Buffer) used for in a processor?

A. Storing video data
B. Ensuring instructions that were executed out-of-order are committed in original program order
C. Buffering internet packets
D. Reordering the bits in a byte

47 Which cooling solution is increasingly common in high-density supercomputers and data centers?

A. Passive heatsinks only
B. Liquid Cooling / Immersion Cooling
C. Standard desk fans
D. Open windows

48 A Neuromorphic processor is designed to mimic:

A. The structure of DNA
B. Biological neural networks (the human brain)
C. Planetary orbits
D. Quantum mechanics

49 What is the Green500 list?

A. A list of eco-friendly laptops
B. A ranking of supercomputers based on energy efficiency (FLOPS per Watt)
C. A list of recyclable computer parts
D. The top 500 cheapest computers

50 In the context of latest processor trends, what is Ray Tracing hardware acceleration?

A. Tracing the physical location of the CPU
B. Hardware dedicated to calculating light paths for realistic graphical rendering
C. A method to trace bugs in software
D. Tracing wire connections on a motherboard