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Unit 2 - Practice Quiz

CSE211

1 In a General Register Organization, which component is typically used to select which register's data is placed onto the common bus?

A. Decoder
B. Multiplexer (MUX)
C. Encoder
D. Flip-Flop

2 Which control word field is responsible for selecting the source register for the A-input of the ALU in a general register organization?

A. SELA
B. SELB
C. OPR
D. SELD

3 A stack organized computer uses which address instruction format for arithmetic operations?

A. Three-address instructions
B. Two-address instructions
C. One-address instructions
D. Zero-address instructions

4 In a memory stack where the stack grows towards lower memory addresses, what is the sequence of operations for a PUSH instruction?

A.
B.
C.
D.

5 What is the result of evaluating the Reverse Polish Notation (RPN) expression using a stack?

A. 32
B. 42
C. 50
D. 60

6 Which register holds the address of the top of the stack?

A. PC (Program Counter)
B. IR (Instruction Register)
C. SP (Stack Pointer)
D. ACC (Accumulator)

7 In which addressing mode is the operand specified directly in the instruction?

A. Direct Addressing
B. Indirect Addressing
C. Immediate Addressing
D. Register Addressing

8 Calculate the Effective Address (EA) for Relative Addressing Mode if the Program Counter (PC) = 200 and the address part of the instruction = 50.

A. 150
B. 200
C. 250
D. 10000

9 Which addressing mode is most suitable for handling array data structures?

A. Immediate Addressing
B. Register Addressing
C. Indexed Addressing
D. Implied Addressing

10 In Indirect Addressing Mode, what does the address field of the instruction contain?

A. The operand itself
B. The address of the operand
C. The address of the address of the operand
D. The effective address calculated by the ALU

11 What is the primary characteristic of a RISC (Reduced Instruction Set Computer) architecture regarding instruction length?

A. Variable instruction length
B. Fixed instruction length
C. Length depends on the opcode
D. Length depends on the addressing mode

12 Which of the following is a characteristic of CISC (Complex Instruction Set Computer) architecture?

A. Large number of registers
B. Hardwired control unit
C. Variable format instructions
D. Single cycle execution

13 In RISC architecture, most operations are performed in:

A. Memory
B. Registers
C. I/O devices
D. Cache only

14 Which control unit implementation is typically found in CISC architectures?

A. Hardwired Control
B. Microprogrammed Control
C. Pipelined Control
D. Software Control

15 A Three-Address Instruction format looks like: ADD R1, A, B. What does this instruction do?

A.
B.
C.
D.

16 Which instruction format implies the use of the Accumulator register?

A. Three-address
B. Two-address
C. One-address
D. Zero-address

17 In the context of data transfer, what does DMA stand for?

A. Direct Memory Allocation
B. Direct Memory Access
C. Dual Memory Access
D. Dynamic Memory Access

18 Which data transfer method involves the CPU constantly checking the status of the I/O device?

A. Interrupt-driven I/O
B. DMA
C. Programmed I/O (Polling)
D. Serial Transfer

19 During a DMA transfer, who controls the system bus?

A. The CPU
B. The DMA Controller
C. The Main Memory
D. The I/O Device

20 What is Cycle Stealing in the context of DMA?

A. The CPU takes cycles from the DMA controller.
B. The DMA controller transfers one word at a time by borrowing a bus cycle from the CPU.
C. The DMA controller halts the CPU for the entire duration of the block transfer.
D. The Operating System steals cycles from idle processes.

21 Which type of interrupt is initiated by an instruction within the program (e.g., division by zero)?

A. External Interrupt
B. Hardware Interrupt
C. Internal Interrupt (Trap)
D. Maskable Interrupt

22 What is the function of the Processor Status Word (PSW)?

A. To hold the next instruction address
B. To store the top of the stack
C. To hold the current status of the CPU, including condition flags
D. To decode the instruction opcode

23 Which flag in the PSW is set if an arithmetic result is zero?

A. C (Carry)
B. S (Sign)
C. Z (Zero)
D. V (Overflow)

24 In a 2's complement system, which flag indicates an overflow condition for signed arithmetic?

A. C (Carry)
B. Z (Zero)
C. V (Overflow)
D. P (Parity)

25 The Sign Flag (S) in the PSW usually copies which bit of the result?

A. The Least Significant Bit (LSB)
B. The Most Significant Bit (MSB)
C. The middle bit
D. The parity bit

26 What happens to the Program Counter (PC) when a subroutine is called using a CALL instruction?

A. It is reset to 0.
B. Its content (return address) is pushed onto the stack.
C. It remains unchanged.
D. It is decremented.

27 What is a Vectored Interrupt?

A. An interrupt that always goes to a fixed memory location.
B. An interrupt where the device supplies the address (or vector) of the interrupt service routine.
C. An interrupt caused by a vector processor.
D. An interrupt that cannot be disabled.

28 Which addressing mode is often used to access the operand when the address is computed by adding a constant value to the contents of the Program Counter?

A. Register Indirect
B. Relative Addressing
C. Indexed Addressing
D. Immediate Addressing

29 In the instruction format, the Opcode specifies:

A. The location of the operand
B. The operation to be performed
C. The address of the next instruction
D. The priority of the interrupt

30 What is the primary advantage of using General Register Organization over Accumulator-based organization?

A. Simpler hardware
B. Faster memory access
C. Reduced traffic to memory and flexible programming
D. Smaller instruction size

31 Which component manages the priority of simultaneous interrupts?

A. ALU
B. DMA Controller
C. Priority Interrupt Controller
D. Program Counter

32 The Auto-increment addressing mode is useful for:

A. Accessing a single variable
B. Accessing constants
C. Iterating sequentially through a block of data
D. Branching to subroutines

33 In RISC, the register file is typically:

A. Small (less than 8 registers)
B. Large (32 or more registers)
C. Non-existent
D. Only used for floating point

34 Which term describes the overlapping of instruction execution phases to increase throughput?

A. Polling
B. Pipelining
C. Interrupts
D. Direct Memory Access

35 In Base Register Addressing, the effective address is calculated as:

A.
B.
C.
D.

36 What happens when a stack Overflow occurs?

A. The stack is empty.
B. An attempt is made to push data into a full stack.
C. An attempt is made to pop data from an empty stack.
D. The stack pointer becomes zero.

37 Which transfer mode uses Handshaking signals (Request/Acknowledge)?

A. Synchronous Transfer
B. Asynchronous Transfer
C. Isochronous Transfer
D. Clocked Transfer

38 The RET (Return) instruction at the end of a subroutine typically:

A. Jumps to the start of memory
B. Pops the return address from the stack into the PC
C. Clears the Accumulator
D. Resets the Stack Pointer

39 A RISC processor aims to achieve a CPI (Cycles Per Instruction) of approximately:

A. 1
B. 5
C. 10
D. 0.1

40 In Implied Addressing Mode, the operand is:

A. Specified in the instruction
B. Stored in the memory
C. Implicitly defined by the instruction definition (e.g., CMA complements Accumulator)
D. Located at the address in the Index Register

41 The collection of all status bits (flags) and control bits is often referred to as:

A. ALU
B. Register File
C. CCR (Condition Code Register) or PSW
D. MAR (Memory Address Register)

42 Which of the following instructions is likely to be found in a CISC machine but not a RISC machine?

A. LOAD R1, A
B. ADD R1, R2, R3
C. MOV A, M[SI+100]
D. STORE R2, B

43 What is the logic equation for the Carry Flag (C) typically generated by an adder?

A. End carry out of the MSB position
B. XOR of the last two carries
C. Result equals zero
D. MSB of the result

44 In the context of Interrupts, what does Masking mean?

A. Deleting the interrupt
B. Temporarily ignoring or disabling specific interrupts
C. Executing the interrupt immediately
D. Hiding the data bus

45 Which register is used to point to the next instruction to be fetched?

A. IR
B. PC
C. MAR
D. MDR

46 The Burst Mode in DMA transfer:

A. Transfers a block of data continuously until completion
B. Transfers one byte and releases the bus
C. Is slower than cycle stealing
D. Requires CPU intervention for every byte

47 Which of the following is NOT a typical field in an instruction format?

A. Opcode
B. Mode Field
C. Address Field
D. Date Field

48 Logic Shift Left (LSL) by 1 bit is equivalent to:

A. Division by 2
B. Multiplication by 2
C. Addition of 2
D. Subtraction of 2

49 Which addressing mode uses the equation , where the PC then increments?

A. Immediate
B. Direct (Absolute)
C. Indirect
D. Register

50 What distinguishes Supervisor Mode (or Kernel Mode) from User Mode in the PSW?

A. Supervisor mode allows execution of privileged instructions.
B. User mode runs faster.
C. Supervisor mode consumes less power.
D. There is no difference.