1In the basic computer instruction format, if the mode bit (I) is 1, what type of addressing is used?
A.Direct Addressing
B.Indirect Addressing
C.Immediate Addressing
D.Register Addressing
Correct Answer: Indirect Addressing
Explanation:In the basic computer instruction format, the most significant bit (bit 15) is the mode bit. If , it is Direct Addressing. If , it is Indirect Addressing.
Incorrect! Try again.
2Which register holds the address of the next instruction to be read from memory after the current instruction is executed?
A.Instruction Register (IR)
B.Accumulator (AC)
C.Program Counter (PC)
D.Data Register (DR)
Correct Answer: Program Counter (PC)
Explanation:The Program Counter (PC) keeps track of the execution of the program and always holds the address of the next instruction to be fetched.
Incorrect! Try again.
3What is the size of the Accumulator (AC) in a basic computer with a 16-bit instruction code?
A.8 bits
B.12 bits
C.16 bits
D.32 bits
Correct Answer: 16 bits
Explanation:The Accumulator (AC) is a processor register that operates on data. In a standard basic computer architecture (like the Mano machine) where the data word is 16 bits, the AC is also 16 bits.
Incorrect! Try again.
4Which component is used to select one of the registers to transfer information onto the common bus?
A.Decoder
B.Multiplexer (MUX)
C.Encoder
D.Flip-Flop
Correct Answer: Multiplexer (MUX)
Explanation:A common bus system using multiplexers employs selection lines () to select specific register outputs to be placed on the bus lines.
Incorrect! Try again.
5In a common bus system with 8 registers, how many selection lines are required for the multiplexers?
A.1
B.2
C.3
D.8
Correct Answer: 3
Explanation:To select one out of 8 inputs (), 3 selection lines () are required.
Incorrect! Try again.
6What is the Effective Address (EA) in the context of instruction codes?
A.The address of the instruction itself
B.The address of the operand in a computation-type instruction
C.The content of the Accumulator
D.The address of the next instruction
Correct Answer: The address of the operand in a computation-type instruction
Explanation:The Effective Address (EA) is the actual memory address where the operand (data) required for the instruction is stored.
Incorrect! Try again.
7Which logic gate is typically used to construct a three-state buffer?
A.AND gate
B.OR gate
C.NAND gate
D.Buffer gate with a control input
Correct Answer: Buffer gate with a control input
Explanation:A three-state buffer (or tri-state buffer) is a logic gate that exhibits three states: logic 0, logic 1, and high impedance (open circuit), controlled by an enable input.
Incorrect! Try again.
8The operation represents:
A.Writing to memory
B.Reading from memory
C.Clearing the Data Register
D.Incrementing the Address Register
Correct Answer: Reading from memory
Explanation:This notation implies transferring the content of the memory location specified by the Address Register (AR) into the Data Register (DR), which corresponds to a Read operation.
Incorrect! Try again.
9In the basic computer, an instruction is stored in the Instruction Register (IR). Which bits of the IR represent the Operation Code (Opcode)?
A.Bits 0 - 11
B.Bits 12 - 14
C.Bit 15
D.Bits 0 - 15
Correct Answer: Bits 12 - 14
Explanation:In the standard 16-bit basic computer instruction format, bits 0-11 are the address, bits 12-14 are the opcode, and bit 15 is the addressing mode.
Incorrect! Try again.
10A Register Reference instruction is identified by which of the following conditions?
A.
B. and
C. and
D.
Correct Answer: and
Explanation:When the opcode bits (12-14) are all 1s (111), the decoder output is 1. If the mode bit (bit 15) is 0, it is a Register Reference instruction. If , it is an I/O instruction.
Incorrect! Try again.
11The Sequence Counter (SC) is used to:
A.Count the number of instructions executed
B.Generate timing signals
C.Store the address of the next instruction
D.Perform arithmetic operations
Correct Answer: Generate timing signals
Explanation:The Sequence Counter (SC) is a 4-bit binary counter connected to a 4x16 decoder to produce timing signals through that control the sequence of operations.
Incorrect! Try again.
12Which timing signal is active during the Fetch phase of the instruction cycle where ?
A.
B.
C.
D.
Correct Answer:
Explanation:The fetch cycle starts at . The transfer of the address from PC to AR occurs at time ().
Incorrect! Try again.
13During the Decode phase (), which of the following operations occurs?
A.
B.
C.Decoding of Opcode and Address calculation
D.Execution of the ALU operation
Correct Answer: Decoding of Opcode and Address calculation
Explanation:At , the opcode in is decoded, the indirect bit is checked, and the effective address logic is prepared.
Incorrect! Try again.
14The hexadecimal code 7800 in a basic computer corresponds to which instruction?
A.CLA (Clear Accumulator)
B.CMA (Complement Accumulator)
C.HLT (Halt)
D.INC (Increment Accumulator)
Correct Answer: CLA (Clear Accumulator)
Explanation:Register reference instructions start with hex digit 7. The binary for CLA is typically defined as 0111 1000 0000 0000, which is 7800 in hexadecimal.
Incorrect! Try again.
15Which register is assumed to receive the result of an arithmetic operation in a One-Address instruction format?
A.Memory
B.Program Counter
C.Accumulator (AC)
D.Instruction Register
Correct Answer: Accumulator (AC)
Explanation:In a single-accumulator organization (One-Address format), the Accumulator is implicitly the destination and one of the sources for arithmetic operations.
Incorrect! Try again.
16What is the function of the ISZ (Increment and Skip if Zero) instruction?
A.Increments PC if AC is zero
B.Increments memory word and skips next instruction if result is zero
C.Increments AC and branches
D.Skips the next instruction unconditionally
Correct Answer: Increments memory word and skips next instruction if result is zero
Explanation:ISZ reads a word from memory, increments it, writes it back, and if the result is 0, increments the Program Counter (PC) to skip the next instruction.
Incorrect! Try again.
17The BSA (Branch and Save Return Address) instruction is primarily used for:
A.Conditional branching
B.Implementing loops
C.Subroutine calls
D.Input/Output operations
Correct Answer: Subroutine calls
Explanation:BSA saves the return address (current PC) into the memory location specified by the effective address and branches to the following location. This allows the program to return after a subroutine.
Incorrect! Try again.
18Which micro-operation clears the Sequence Counter (SC) to 0?
A.
B. input of SC is activated
C.
D.All of the above depending on the instruction completion
Correct Answer: All of the above depending on the instruction completion
Explanation:The SC is cleared to 0 to restart the instruction cycle (fetch phase). This happens at the end of every instruction execution (e.g., or ).
Incorrect! Try again.
19In the Little Man Computer (LMC) model, the Mailbox represents which hardware component?
A.CPU
B.Memory (RAM)
C.Input Device
D.Output Device
Correct Answer: Memory (RAM)
Explanation:In the LMC analogy, the mailboxes are where instructions and data are stored, representing the computer's memory.
Incorrect! Try again.
20In LMC, the mnemonic STA corresponds to:
A.Stop the program
B.Subtract from Accumulator
C.Store Accumulator contents to memory
D.Input to Accumulator
Correct Answer: Store Accumulator contents to memory
Explanation:STA stands for Store Accumulator. It copies the value currently in the calculator (Accumulator) to a specific mailbox (Memory).
Incorrect! Try again.
21The Input Register (INPR) usually holds:
A.8-bit alphanumeric input information
B.16-bit address information
C.Control signals
D.Arithmetic results
Correct Answer: 8-bit alphanumeric input information
Explanation:INPR is typically an 8-bit register used to receive a character from an input device.
Incorrect! Try again.
22Which flag is set to 1 when new information is available in the input device?
A.FGO (Output Flag)
B.FGI (Input Flag)
C.IEN (Interrupt Enable)
D.R (Interrupt Flip-flop)
Correct Answer: FGI (Input Flag)
Explanation:FGI is the Input Flag. It is set to 1 when the input device has placed new data into the Input Register (INPR).
Incorrect! Try again.
23What is the purpose of the IEN (Interrupt Enable) flip-flop?
A.To indicate an error has occurred
B.To store the return address
C.To allow or disallow the programmer to control interrupts
D.To signal the end of a program
Correct Answer: To allow or disallow the programmer to control interrupts
Explanation:IEN is used to enable (1) or disable (0) the interrupt facility. If IEN=0, flags FGI and FGO are ignored.
Incorrect! Try again.
24Which condition triggers the Interrupt Cycle in a basic computer?
A.
B.
C.
D.
Correct Answer:
Explanation:An interrupt is initiated at the end of an execution cycle (when not in T0-T2) if Interrupts are Enabled (IEN=1) and either the Input or Output flag is set.
Incorrect! Try again.
25During an interrupt cycle, the return address (content of PC) is typically stored at:
A.Memory location 0
B.The top of the stack
C.A special register named TR
D.Memory location 100
Correct Answer: Memory location 0
Explanation:In the standard basic computer model (Mano), the interrupt cycle stores the return address in memory location 0 and branches to location 1.
Incorrect! Try again.
26Which register is NOT connected directly to the common bus system?
A.DR (Data Register)
B.AC (Accumulator)
C.INPR (Input Register)
D.OUTR (Output Register)
Correct Answer: INPR (Input Register)
Explanation:In many basic architectures (like Mano), the INPR often feeds directly into the AC or has a dedicated path, but strictly speaking in the common bus diagram, the INPR is connected to the bus, but the Accumulator (AC) often has its input from the Adder/Logic logic, not directly from the bus (though it can output to the bus). However, in the specific Mano Bus design, INPR puts data on the bus. Wait, strictly, the OUTR usually receives data from the bus but does not place data onto the bus (it outputs to the device). Let's refine based on standard diagrams: The Adder and Logic circuit drives the AC input. The Accumulator output goes to the bus. OUTR inputs from the bus, but its output goes to the external device, not the bus. Therefore, OUTR output is not connected to the bus.
Incorrect! Try again.
27What happens during the micro-operation ?
A.The program counter is cleared.
B.The program counter is incremented to point to the next instruction.
C.The instruction is decoded.
D.The instruction is executed.
Correct Answer: The program counter is incremented to point to the next instruction.
Explanation:During the fetch phase (), the PC is incremented so it is ready to fetch the sequential instruction in the next cycle.
Incorrect! Try again.
28Which instruction typically implies ?
A.ADD
B.LDA
C.AND
D.BUN
Correct Answer: AND
Explanation:The AND instruction performs a bitwise AND operation between the Accumulator and the memory word at the effective address.
Incorrect! Try again.
29In the instruction cycle state diagram, what determines the transition from the Decode phase to the Indirect phase?
A.
B. and
C.
D.
Correct Answer: and
Explanation:If it is a memory reference instruction () and the mode bit is Indirect (), the control goes to the indirect address processing state.
Incorrect! Try again.
30If the BUN (Branch Unconditionally) instruction is executed, what happens to the PC?
A.
B. Effective Address
C.
D. remains unchanged
Correct Answer: Effective Address
Explanation:BUN updates the Program Counter with the Effective Address provided in the instruction, causing the program to jump to that location.
Incorrect! Try again.
31What is the purpose of the Temporary Register (TR) in the basic computer?
A.To hold temporary data during processing
B.To store the instruction code
C.To interface with I/O devices
D.To count clock pulses
Correct Answer: To hold temporary data during processing
Explanation:The TR is a scratchpad register used to hold temporary data required during arithmetic or logic operations.
Incorrect! Try again.
32The Little Man Computer (LMC) uses which number system for its operation visible to the user?
A.Binary
B.Hexadecimal
C.Decimal
D.Octal
Correct Answer: Decimal
Explanation:The LMC is a simplified model that operates on decimal numbers (usually 000 to 999) to make understanding computer architecture easier for students.
Incorrect! Try again.
33The control unit of a basic computer acts as the:
A.Memory storage
B.Nerve center handling timing and signals
C.Power supply
D.Arithmetic calculator
Correct Answer: Nerve center handling timing and signals
Explanation:The Control Unit generates timing and control signals to coordinate the operations of the datapath, memory, and I/O.
Incorrect! Try again.
34Hardwired control units are implemented using:
A.Control Memory (ROM)
B.Software micro-routines
C.Logic gates, flip-flops, and decoders
D.Cloud servers
Correct Answer: Logic gates, flip-flops, and decoders
Explanation:Hardwired control uses fixed combinational logic circuits and flip-flops to generate control signals, offering high speed but less flexibility.
Incorrect! Try again.
35Which signal controls the Read operation from Memory?
A.Write
B.Read
C.Load
D.Clear
Correct Answer: Read
Explanation:The Read control signal enables the memory to place the data from the location specified by AR onto the bus.
Incorrect! Try again.
36In a Direct Addressing instruction (), the address part of the instruction equals:
A.The pointer to the address
B.The Effective Address (EA)
C.The operand itself
D.Zero
Correct Answer: The Effective Address (EA)
Explanation:In direct addressing, the address field contains the actual address where the operand is stored.
Incorrect! Try again.
37What does the LMC mnemonic BRP stand for?
A.Branch if Positive
B.Branch if Previous
C.Break Program
D.Branch Return Pointer
Correct Answer: Branch if Positive
Explanation:BRP is a conditional branch in LMC. The program branches if the value in the Accumulator is zero or positive.
Incorrect! Try again.
38The ION instruction in the basic computer:
A.Turns the computer On
B.Sets the Interrupt Enable (IEN) flip-flop to 1
C.Inputs a Number
D.Initiates Output Node
Correct Answer: Sets the Interrupt Enable (IEN) flip-flop to 1
Explanation:ION (Interrupt On) is an I/O instruction that sets IEN to 1, allowing the processor to acknowledge interrupts.
Incorrect! Try again.
39If and , the instruction bits 0-11 specifying the I/O operation are executed when?
A.
B.
C.
D.
Correct Answer:
Explanation:For I/O instructions (), the execution occurs at timing signal .
Incorrect! Try again.
40Which component stores the result of the ADD micro-operation ?
A.DR
B.AC
C.Memory
D.PC
Correct Answer: AC
Explanation:The result of the addition is transferred back into the Accumulator (AC).
Incorrect! Try again.
41The Cout (Carry Out) from the Adder-Logic circuit is usually transferred to:
A.The E (Extended Accumulator) flip-flop
B.The PC
C.The Memory
D.The INPR
Correct Answer: The E (Extended Accumulator) flip-flop
Explanation:In the basic computer design, the E flip-flop holds the carry bit resulting from arithmetic operations in the AC.
Incorrect! Try again.
42Micro-operations are:
A.High-level language commands
B.Elementary operations performed on data in registers
C.Operating system calls
D.Complex mathematical algorithms
Correct Answer: Elementary operations performed on data in registers
Explanation:A micro-operation is an elementary operation performed during one clock pulse on the information stored in one or more registers.
Incorrect! Try again.
43In the LMC, the INP instruction:
A.Prints the accumulator value
B.Takes user input and stores it in the Accumulator
C.Takes user input and stores it in Memory
D.Increments the pointer
Correct Answer: Takes user input and stores it in the Accumulator
Explanation:INP halts the LMC to wait for user input, which is then placed into the Accumulator/Calculator.
Incorrect! Try again.
44The decoder outputs through are generated based on:
A.The Sequence Counter (SC)
B.The Opcode bits of IR (bits 12-14)
C.The Address bits of AR
D.The Mode bit
Correct Answer: The Opcode bits of IR (bits 12-14)
Explanation:A 3x8 decoder takes the 3 opcode bits from the Instruction Register and activates one of the outputs to .
Incorrect! Try again.
45Which of the following is NOT a phase of the instruction cycle?
A.Fetch
B.Decode
C.Execute
D.Compile
Correct Answer: Compile
Explanation:The instruction cycle consists of Fetch, Decode, and Execute (and potentially Interrupt). Compilation is a software process that converts source code to machine code before execution.
Incorrect! Try again.
46A Bus Grant signal is part of:
A.The ALU
B.The Memory array
C.Arbitration logic in a bus system
D.The Instruction Register
Correct Answer: Arbitration logic in a bus system
Explanation:While less emphasized in the simplest 'Basic Computer', in general Bus systems, arbitration (Request/Grant) is used to determine which device controls the bus.
Incorrect! Try again.
47The SKI (Skip on Input Flag) instruction checks:
A.If
B.If
C.If
D.If
Correct Answer: If
Explanation:SKI is an I/O instruction that checks the Input Flag (FGI). If it is set (1), the PC is incremented to skip the next instruction.
Incorrect! Try again.
48To perform a subtraction in the basic computer using the Adder/Logic circuit, the computer usually performs:
A.Direct hardware subtraction
B.2's complement addition
C.Multiplication by -1
D.Bitwise OR
Correct Answer: 2's complement addition
Explanation:Digital computers typically use complement arithmetic. is performed as .
Incorrect! Try again.
49If the load (LD) input of a register is 0, what happens when the clock pulse arrives?
A.The register is cleared
B.The register loads data from the bus
C.The register content remains unchanged
D.The register increments
Correct Answer: The register content remains unchanged
Explanation:Registers with parallel load capability usually retain their current state if the Load control input is inactive (0) during a clock pulse.
Incorrect! Try again.
50What is the primary motivation for using a Common Bus System?
A.To increase the number of registers
B.To reduce the number of wires and connections between registers
C.To speed up the clock frequency
D.To eliminate the need for memory
Correct Answer: To reduce the number of wires and connections between registers
Explanation:A common bus provides a shared path for data transfer, significantly reducing the wiring complexity compared to point-to-point connections between every register pair.
Incorrect! Try again.
Give Feedback
Help us improve by sharing your thoughts or reporting issues.