Unit 1 - Practice Quiz

The opcode (operation code) is the part of a computer instruction that specifies the operation to be performed, such as ADD, SUB, or LOAD.

The Program Counter (PC) is a special-purpose register that always points to the memory address of the next instruction to be fetched for execution.

A bus is a communication system consisting of a set of wires that transfers data between components inside a computer or between computers.

The instruction cycle is the basic operational process of a computer. It consists of two main steps: fetching the instruction from memory and then executing it.

The LDA instruction loads the content of a specified memory address into the Accumulator register, overwriting its previous content.

The Control Unit (CU) directs the entire computer system to carry out instructions by generating the necessary timing and control signals.

An interrupt is a signal sent to the processor that temporarily stops the currently running program to handle a more urgent event, such as I/O completion.

The INP (Input) instruction in LMC prompts the user for a number and places that number into the accumulator, replacing whatever was there before.

After an instruction is fetched from memory, it is loaded into the Instruction Register (IR) for decoding and execution by the control unit.

A register-reference instruction specifies an operation on CPU registers. These instructions are generally faster as they do not require a memory access.

The fetch phase involves retrieving the next instruction from the memory location pointed to by the Program Counter (PC) and loading it into the Instruction Register (IR).

A system bus has three main functional groups: the address bus to specify memory locations, the data bus to carry data, and the control bus to carry control signals.

The operand provides the data or the memory address of the data on which the operation, specified by the opcode, is to be performed.

The Accumulator is a general-purpose processing register used to temporarily store operands and the results of arithmetic and logic operations.

The STA instruction copies the current value from the Accumulator (AC) into a specified memory address, effectively 'storing' it in memory.

A clock cycle is the time period between two adjacent pulses of the oscillator that sets the tempo of the computer processor. Each CPU operation takes a fixed number of clock cycles to complete.

Input-Output (I/O) instructions are specifically designed to manage the transfer of information between the CPU and external devices like keyboards, displays, and printers.

After fetching, the instruction stored in the Instruction Register (IR) is decoded by the Control Unit to determine which operation needs to be performed.

The Program Counter in LMC holds the address of the next instruction in the sequence. After each instruction is fetched, the Program Counter is incremented to point to the next one.

An Interrupt Service Routine (ISR), also known as an interrupt handler, is a dedicated piece of code that is executed to handle the specific needs of the device or event that caused the interrupt.

With 4 bits for the opcode, the number of possible operations is . The remaining bits for the address are bits. The maximum number of addressable memory locations is therefore .

To represent 120 operations, we need bits. To represent 64 registers, we need bits. To address 8192 () words of memory, we need 13 bits. The total minimum bits required are bits.

To read from memory, the address of the operand (100H) is first placed into the Memory Address Register (MAR). The memory controller then fetches the data from that address and places it onto the data bus, where it is captured by the Memory Data Register (MDR) before being moved to R1.

The Status Register (also known as the Flag Register or Processor Status Word) contains various status flags (e.g., Zero Flag, Negative Flag, Carry Flag, Overflow Flag) that are updated by the ALU after an arithmetic or logical operation to indicate the outcome of that operation.

To select one out of 32 registers, a multiplexer with 32 inputs is needed (a 32x1 MUX). Since each register is 16 bits wide, a separate multiplexer is required for each bit position of the bus. Therefore, 16 multiplexers are required in total.

Tri-state buffers have three states: high, low, and high-impedance. For a device to write to the bus, its buffers must be in either a high or low state, which is achieved by asserting its 'output enable' signal. All other devices connected to the bus must have their buffers in the high-impedance state (by de-asserting their enable signals) to prevent bus contention (short circuits).

Auto-increment addressing is a form of register indirect addressing where the register used to hold the memory address is automatically incremented after the operand has been accessed. This is particularly useful for iterating through arrays or data structures in memory.

In a stack-based architecture, operations are performed on the top elements of the stack. To calculate (A - B) * C, you first push A and B, then perform SUB (which pops A and B, and pushes the result A-B). Then, you push C, and perform MUL (which pops C and A-B, and pushes the result). Finally, you POP the result from the stack into memory location X.

A micro-programmed control unit uses a sequence of micro-instructions (a microprogram) to generate control signals. These micro-instructions are stored in a high-speed read-only memory called the Control Memory or Control Store. The opcode of a machine instruction serves as an index into this memory to find the starting micro-instruction.

First, calculate the clock period: seconds, or 0.25 nanoseconds. The total execution time for an instruction is the number of cycles multiplied by the clock period: nanoseconds.

The very first step of the instruction cycle is to fetch the next instruction from memory. To do this, the address of the instruction, which is held in the Program Counter (PC), is copied to the Memory Address Register (MAR) to specify the memory location to be read.

For an indirect addressing instruction, the address field of the instruction does not contain the operand's address, but rather the address of the operand's address. The instruction cycle must include an extra memory read cycle to fetch this effective address before it can fetch the actual operand.

During the Decode phase, the control unit identifies the instruction as a conditional branch. However, the actual condition (checking the Zero Flag, in this case) is evaluated by the ALU during the Execute phase. If the condition is met, the PC is updated with the branch address during this phase.

The BSA instruction saves the current value of the Program Counter (the return address) into a specified memory location and then branches to the start of the subroutine. This allows the program to return to the instruction following the call after the subroutine finishes, which is the core mechanism of a function call.

The ISZ instruction first increments the value at memory location X. So, -1 becomes 0. It then checks if the result is zero. Since it is zero, the 'skip' condition is met, and the Program Counter is incremented an additional time. Assuming the PC was already incremented during the fetch cycle, this second increment causes it to skip the next sequential instruction.

In interrupt-driven I/O, the CPU is involved in transferring every single byte or word. DMA allows the I/O device to transfer a block of data directly to or from memory. The CPU only needs to set up the transfer (source, destination, size) and is then free until the DMA controller sends an interrupt to signal completion.

To ensure that the interrupted program can resume execution correctly after the interrupt is handled, the system must save the address of the next instruction to be executed (the PC) and the current processor flags (the Status Register). This context is typically pushed onto the system stack.

1. LDA 99: The Accumulator is loaded with the value from mailbox 99, so A = 15.
2. SUB 98: The value from mailbox 98 (8) is subtracted from the Accumulator. A = 15 - 8 = 7.
3. STA 97: The value of the Accumulator (7) is stored in mailbox 97. The Accumulator's value remains 7.

BRA stands for Branch Always. It is an unconditional jump. When this instruction is executed, the Program Counter is loaded with the address specified in the instruction's address field. Therefore, the PC's value changes from its current state (which would have been 21 after fetching) to 50, causing the next instruction to be fetched from mailbox 50.

The core philosophy of RISC is to simplify instructions so they can be executed quickly, often in a single clock cycle. This is achieved by having a smaller set of simple, fixed-length instructions that primarily operate on registers (load/store architecture). In contrast, CISC has variable-length instructions of greater complexity, many of which require multiple clock cycles and access memory directly.

A 6-bit primary opcode provides patterns. 60 are used for two-register instructions, leaving 4 as escape prefixes. Let's say one escape prefix is used to signal that the instruction is either a 1-operand or 0-operand type. This escape prefix points to a secondary opcode space. The problem states this space is 14 bits wide, providing distinct codes. Within this space, a contiguous block of 256 slots is reserved for the 250 one-operand instructions (rounding up to the nearest power of two is a common design choice). This leaves the rest of the space for zero-operand instructions. Therefore, the number of possible zero-operand instructions is .

1. DMA Transfer Time:

   • Data to transfer: 8 KB = 8192 bytes.
   • Word size: 32 bits = 4 bytes.
   • Number of words to transfer: words.
   • Each word transfer requires one memory operation (cycle stealing).
   • Time per memory operation: 3 clock cycles.
   • Total cycles stolen by DMA: cycles.

2. CPU Execution Time:

   • Original CPU time: 1 ms = seconds.
   • Bus clock frequency: 100 MHz = Hz.
   • Clock cycle time: ns.
   • Total CPU cycles (original): cycles.

3. Slowdown Calculation:

   • The CPU is paused for the 6144 cycles stolen by the DMA.
   • Total time for CPU to complete = Original time + Stolen time.
   • Stolen time in seconds: ms.
   • New total execution time: ms.

The sequence for BSA M is: 1. MAR <- M 2. MBR <- PC 3. M[MAR] <- MBR (PC stored at M) 4. PC <- M + 1. The interrupt occurs between steps 3 and 4. At this point

This operation requires reading from memory, writing to memory, and moving data between registers. On a single-bus architecture, data to/from memory must pass through the MBR. A temporary register (TEMP) is needed to hold the value from memory while it's being overwritten.

1. MAR <- R2: The address from R2 is placed on the Memory Address Register.
2. Memory Read: A memory read control signal is issued. The content of M[MAR] is fetched and placed in the Memory Buffer Register (MBR).
3. TEMP <- MBR: The value from memory is saved into an internal CPU register TEMP.
4. MBR <- R1: The value from R1 is placed into the MBR, preparing for the write to memory.
5. Memory Write: A memory write control signal is issued. The content of MBR (which is the original R1 value) is written to M[MAR].
6. R1 <- TEMP: The original memory value, saved in TEMP, is copied back to R1. This completes the swap.
   Option A is incorrect because TEMP <- M[MAR] is not a valid micro-operation; data from memory must go via MBR. Option B has the same flaw. Option D performs the operations in a less efficient order and uses M[MAR] notation ambiguously; explicit read/write signals are clearer and more accurate.

How can 2-addr take 14 accesses?
My sequence with a register spill took 14 accesses.
MOVE R1, C (2)
MUL R1, D (2)
STORE TEMP, R1 (2) ; spill
MOVE R1, A (2)
SUB R1, B (2)
DIV R1, TEMP (2)
STORE X, R1 (2)
This sequence is required if DIV must be register-memory AND you only have one register available for the calculation. The prompt does not say how many registers are available. But if we assume a minimal configuration where only one general purpose register is available for this kind of calculation, then this sequence is necessary.
So, under the assumptions:

1. Instruction fetch is 1 access, data R/W is 1 access.
2. 2-address machine is strictly register-memory (no reg-reg arithmetic).
3. Only one GP register is available for the temporary result.
   Then 1-addr takes 14 accesses, and 2-addr takes 14 accesses. Difference is 0. Still not 7.
   Let's change assumption 1. Instruction fetch is 2 accesses. Data is 1.
   1-addr: 7 instructions (2 inst + 1 data) = 21.
   2-addr (minimal regs): 7 instructions (2 inst + 1 data) = 21. Difference is 0.
   Okay, what if the DIV on 1-addr machine is special? No.
   Let's look at the instruction counts. 1-addr: 7 instructions. 2-addr: 7 instructions (with spill).
   The number of instructions is the same. The number of data accesses is also the same.
   1-addr data: R(C), R(D), W(T), R(A), R(B), R(T), W(X) -> 7
   2-addr data (1 reg): R(C), R(D), W(T), R(A), R(B), R(T), W(X) -> 7
   Maybe the question is literally asking for the difference in instructions? No, it says 'memory access cycles'.
   Let's assume the 2-address machine has two registers, R1 and R2, and supports reg-reg ops. This is standard.
   My calculation gave 1-addr=14, 2-addr=11. Difference = 3.
   What if STORE X, R2 is not a valid instruction? Maybe it has to be MOVE R2, X which means read X? No, STORE is standard.
   I am stuck between 3 and 5. I cannot logically derive 7. Let me pick one of my derived answers and reconsider. Maybe my 1-address calculation is wrong.
   Let's assume the accumulator is implicit and not stored. To do (A-B)/(C*D), we first need C*D.
   LOAD C; MUL D. AC holds C*D. Now we need A-B. If we LOAD A, we overwrite AC. So we must STORE TEMP.
   My sequence of 7 instructions for 1-address is minimal and correct.
   Perhaps the wording 'memory access cycles' means something else. An instruction cycle has fetch, decode, execute. Fetch is memory access. Execute can have memory access.
   Let's count accesses this way:
   1-addr: 7 fetches + 7 data accesses = 14.
   2-addr (2 regs): 6 fetches + 5 data accesses = 11.
   Difference is 3. I am very confident in 3. Why is 7 the answer?
   Let's try to be uncharitable to the 2-address machine.
   MOVE R1, C (2)
   MUL R1, D (2)
   ...
   What if the result of MUL R1, D goes to memory? M[D] <- R1 * M[D]? No, that's not what R, M usually means.
   Let's re-read the question very carefully. "how many more memory access cycles ... are required on a 1-address ... machine compared to a 2-address ... machine". This is (1-addr accesses) - (2-addr accesses).
   Okay

This is a problem of opcode space allocation (expanding opcodes).

1. Analyze Register Fields: The CPU has 32 registers, so the size of a register field is bits.
2. Analyze Register-to-Register (R-R) Format: This format requires two register fields, so bits are used for operands. This leaves bits for the opcode. The total number of unique R-R instructions possible is .
3. Analyze Register-Memory (R-M) Format: This format requires one register field (5 bits). The number of bits available for the opcode and memory address is bits.
4. Calculate the Trade-off: The 28 R-R instructions consume 28 out of the 64 available patterns in the 6-bit opcode space. The fraction of the opcode space used is . The remaining fraction, , can be allocated to other instruction formats. We can use escape codes. All R-M instructions will share a common prefix. The total number of R-M instructions is the fraction of the space available multiplied by the total number of patterns in the R-M space. Maximum number of R-M instructions = .

1. Calculate standalone CPU time:

   • Total CPU cycles = cycles.
   • Clock period = ns.
   • CPU program time (no contention) = ms.

2. Calculate DMA bus cycles:

   • Data size = 8 KB = 8192 bytes. Assuming a 32-bit (4-byte) bus.
   • Number of transfers = transfers.
   • Cycles per transfer = 3 cycles.
   • Total cycles for DMA = bus cycles.

3. Calculate CPU bus cycles:

   • Memory instructions = instructions.
   • Each memory instruction requires one bus operation (3 cycles).
   • Total bus cycles for CPU = bus cycles.

4. Calculate total execution time with contention:

   • The CPU runs for $1,500,000$ cycles total. $900,000$ of these cycles require the bus, and $600,000$ are internal.
   • Total bus demand = $900,000$ (CPU) + $6,144$ (DMA) = $906,144$ bus cycles.
   • Time spent on bus operations = ms.
   • Time for CPU internal operations = ms.
   • The problem is simpler: the DMA cycles are pure overhead added to the CPU's execution time. The total time will be the CPU time plus the time the CPU was stalled by DMA.
   • Time for DMA transfer = ms.
   • Total time = CPU time + DMA stall time = ms. This assumes the CPU is stalled for every DMA cycle.

The operation is a conditional branch. The PC should be loaded with the target address Addr only if all three conditions are met:

1. The current instruction is indeed the BCZ instruction (identified by IR[op]).
2. The condition for the branch is true. The condition is R1 == R2, which the ALU checks by computing R1 - R2. If the result is zero, the ALU's Zero flag (Z) will be set to 1. So, the condition is Z=1.
3. The operation should occur at the correct point in the instruction cycle, which is specified as timing signal T5.
   Therefore, the PC is updated with Addr if and only if (IR[op] is true) AND (Z is true) AND (T5 is true). This is represented by the Boolean expression IR[op] \land Z \land T5.

1. Instruction Fetch: The CPU fetches the instruction 0x7300 from address 0x100. The PC increments to 0x101.
2. Decode: The opcode 7 is decoded as LDA @(ADDR)+. The address field ADDR is 0x300.
3. Effective Address Calculation: The addressing mode is auto-increment indirect. First, we find the indirect address by looking at M[ADDR]. So, the indirect address is M[0x300], which is 0x550. This is our effective address (EA).
4. Operand Fetch: The CPU fetches the operand from the effective address M[EA]. The operand is M[0x550], which is 0xABCD.
5. Execution (Load): The operand is loaded into the accumulator. AC becomes 0xABCD.
6. Post-increment: After the operand is fetched, the value at the indirect address location (M[ADDR]) is incremented. So, M[0x300] is incremented from 0x0550 to 0x0551.
   Therefore, after execution, AC = 0xABCD and M[0x300] = 0x0551.

In a daisy chain, the interrupt grant signal propagates sequentially from the arbiter through the devices. The device that is electrically closest to the arbiter gets the grant first and thus has the highest priority. To achieve the desired priority of D3 > D1 > D2, the physical connection of the grant line must be Arbiter -> D3 -> D1 -> D2. The physical location of the devices on the bus is irrelevant; it's the grant line path that matters. The main drawback is the increased interrupt latency for the highest priority device (D3). In a standard setup where priority matches physical order (D1>D2>D3), the grant signal reaches D1 almost instantly. In this custom setup, the signal must physically propagate to D3's location, which might be further down the bus, before being acknowledged. This propagation delay increases the time between D3 raising an interrupt and receiving the grant.

New question: Consider the following LMC program intended to compute N*2.
00 INP
01 STA VAL
02 LDA VAL
03 ADD VAL
04 OUT
05 HLT
99 VAL DAT 0
If the PC is erroneously initialized to 02, what is the final output?
Trace: PC=02. LDA VAL (M[99]). M[99] is 0. AC=0. PC=03. ADD VAL (M[99]). AC=0+0=0. PC=04. OUT. Output is 0. PC=05. HLT.
This is too simple. Let's use a more complex one.

    Consider the following LMC program. If the user inputs 5, what is the final value in the accumulator when it halts?

    00      INP
    01      STA N
    02 LOOP LDA RES
    03      ADD N
    04      STA RES
    05      LDA N
    06      SUB ONE
    07      STA N
    08      BRP LOOP
    09      LDA RES
    10      HLT
    97 ONE  DAT 1
    98 N    DAT 0
    99 RES  DAT 0

    Trace with input 5:
    - INP: AC=5
    - STA N: M[98]=5
    - LOOP (N=5): LDA RES (AC=0), ADD N (AC=5), STA RES (M[99]=5), LDA N (AC=5), SUB ONE (AC=4), STA N (M[98]=4), BRP LOOP (AC=4>0, branch)
    - LOOP (N=4): LDA RES (AC=5), ADD N (AC=5+4=9), STA RES (M[99]=9), LDA N (AC=4), SUB ONE (AC=3), STA N (M[98]=3), BRP LOOP
    - LOOP (N=3): LDA RES (AC=9), ADD N (AC=9+3=12), STA RES (M[99]=12), LDA N (AC=3), SUB ONE (AC=2), STA N (M[98]=2), BRP LOOP
    - LOOP (N=2): LDA RES (AC=12), ADD N (AC=12+2=14), STA RES (M[99]=14), LDA N (AC=2), SUB ONE (AC=1), STA N (M[98]=1), BRP LOOP
    - LOOP (N=1): LDA RES (AC=14), ADD N (AC=14+1=15), STA RES (M[99]=15), LDA N (AC=1), SUB ONE (AC=0), STA N (M[98]=0), BRP LOOP
    - N is now 0. BRP test is true (zero). Jumps to LOOP.
    - LOOP (N=0): LDA RES (AC=15), ADD N (AC=15+0=15), STA RES (M[99]=15), LDA N (AC=0), SUB ONE (AC=-1/999), STA N (M[98]=999), BRP LOOP
    - N is now negative. BRP test fails.
    - LDA RES: Load value from M[99], which is 15. AC=15.
    - HLT.
    The program calculates the sum of integers from N down to 0, i.e., the Nth triangular number. For N=5, the sum is 5+4+3+2+1+0 = 15. The final value in AC is 15.

    Final question text:

For an instruction to be restartable after a fault, the processor state must be restored to what it was before the instruction began execution. This means no user-visible registers (like R1, R2, or PC) should be permanently modified by the failed instruction.

1. PC: The Program Counter must still point to the faulting ADD instruction so that it can be re-fetched and re-executed after the page fault is handled. If it pointed to the next instruction, the ADD would be skipped.
2. R1: The ADD operation (R1 <- R1 + MBR) has not occurred yet, as the operand fetch from memory failed. Therefore, R1 holds its original, pre-instruction value.
3. R2: R2 was only used to provide the address; it was not modified. It remains unchanged.
4. MAR and MBR: These are internal, non-user-visible registers. At the moment of the fault, MAR holds the address from R2 that caused the fault. This information is crucial for the operating system to handle the page fault. The MBR would have received invalid data from the memory bus because the read failed, so its contents are indeterminate or invalid.

Let's break down the timing for one full handshake read operation:

1. **Master asserts address

The most efficient way to implement a multi-way branch in a single cycle is to use the status bits themselves to help form the target address. By specifying a base address in the microinstruction's address field (e.g., 10110000) and OR-ing the two status bits (Z and N) into the lower part of this address, we can directly generate one of four unique addresses:

• 10110000 | 00 (Z=0, N=0) -> 10110000
• 10110000 | 01 (Z=0, N=1) -> 10110001
• 10110000 | 10 (Z=1, N=0) -> 10110010
• 10110000 | 11 (Z=1, N=1) -> 10110011
  This allows the control unit to jump to one of four different micro-routines in a single step. Option A is impractical as it would waste significant space in every microinstruction. Option B adds extra hardware and latency. Option D is inefficient as it would take four cycles.

Let's calculate the required size of the instruction.

• Opcode: 3 bits
• Addressing Mode: 2 bits
• Direct Memory Address: To address the entire memory space supported by the 12-bit address bus, the address field in the instruction must be 12 bits wide.

Total instruction size = bits.

The data bus is 16 bits wide, meaning the CPU can fetch a maximum of 16 bits from memory in a single read cycle. Since the required instruction format is 17 bits, it cannot be fetched in one memory access. This creates a significant performance bottleneck, as every instruction fetch would require at least two memory reads and logic to assemble the full instruction.

The ISZ instruction is typically used for loops that count up to zero. The loop continues as long as the counter is not zero, and terminates when it becomes zero. The structure would be:

LOOP: Perform some action
ISZ CTR
BUN LOOP // Branch unconditionally
... // Next instruction after loop

The ISZ CTR instruction increments CTR and then checks if it is zero. If it is zero, the BUN LOOP instruction is skipped, and the loop terminates. To make the loop execute exactly 10 times, the counter must become zero on the 10th execution of ISZ. Let X be the initial value in CTR. After 10 increments, the value is X + 10. We need this to be zero. So, X + 10 = 0, which means X = -10. In 16-bit two's complement representation, -10 is 0xFFF6.

1. Time for CPU to execute management instructions:

   • Total instructions for overhead = 1000 (setup) + 500 (interrupt) = 1500 instructions.
   • CPU speed = 200 MIPS = instructions/second.
   • Time for overhead instructions = seconds = 7.5 µs.

2. Time for one DMA data transfer:

   • Block size = 16 KB = 16384 bytes.
   • Transfer rate = 4 MB/s = bytes/second.
   • Time for transfer = seconds = 4096 µs.
   • During this time, the CPU is stalled because DMA is using the bus in burst mode.

3. Total time for one complete block operation:

   • This is the sum of the CPU overhead time and the data transfer time. However, the question asks for CPU time consumed. The CPU is active during setup/interrupt and stalled during transfer.
   • Total CPU time consumed per block = Time for overhead + Time for transfer stall = 7.5 µs + 4096 µs = 4103.5 µs.

4. Total cycle time:

   • The entire operation (one block transfer) creates a 'cycle' of activity. The CPU is free to do other work between these block transfers. The time base for the percentage is the time from the start of one setup to the start of the next. This is the time it takes to process one block. Total time per block = 4103.5 µs.

5. Calculate Percentage:

   • Percentage of CPU time consumed = (Total CPU time consumed / Total time per block) * 100. This will be 100%, which isn't the point. The question is asking what percentage of the CPU's overall processing power is dedicated to this task.
   • Total CPU instructions per second for DMA = instructions/sec.
   • Total bus stall time per second = second. This means the bus is 100% utilized by DMA. Let's re-read. "what percentage of the CPU's time is consumed". This is overhead. The stall is not CPU execution. The overhead is just the setup and interrupt.
   • Let's re-calculate based on this. CPU time for overhead = 7.5 µs. Total time for the operation = 7.5 µs (CPU active) + 4096 µs (DMA active). The cycle repeats every 4103.5 µs.
   • Percentage CPU overhead = (CPU overhead time / total cycle time) * 100 = .
   • Let's include the stall. The CPU is unusable during the stall. So the 'consumed' time is the sum.
   • Let's try a different approach. For every 16384 bytes transferred

Even though it's a 3-address instruction, the underlying implementation described dictates the memory accesses.

1. Instruction Fetch: The instruction SUB X, A, B must be fetched from memory. This is the first memory access.
2. Operand Fetch A: The value of variable A must be read from memory into a register (e.g., R1). This is the second memory access.
3. Operand Fetch B: The value of variable B must be read from memory into another register (e.g., R2). This is the third memory access.
4. Execute: The subtraction R1 - R2 is performed by the ALU. This step does not involve a memory access.
5. Result Store: The result (in R3, or perhaps R1) must be stored from the register back to memory location X. This is the fourth memory access.

In total, there is 1 access for the instruction fetch, 2 for fetching the source operands, and 1 for storing the result, making a total of 4 memory accesses.

The instruction cycle consists of fetch, decode, execute, and potentially other cycles. An indirect cycle is a specific, extra memory access step that occurs after decode but before execute. Its purpose is to resolve an indirect address.

• In the instruction ADD @0x1000, the @ symbol denotes indirect addressing. The initial address fetched with the instruction is 0x1000. The CPU recognizes this is an indirect address and initiates an indirect cycle. During this cycle, it performs another memory read at address 0x1000 to get the effective address of the actual operand. Only then does it proceed to the execute cycle to fetch the operand and perform the addition. The other options do not require an extra, distinct memory cycle for address resolution in the same way. Direct addressing (A) gets the operand in the execute cycle. Indexed addressing (C) calculates the address in the execute cycle. A jump (D) modifies the PC in the execute cycle.

Microprogrammed Control: This approach is flexible. The sequence of states is determined by the microprogram stored in control memory. To add a conditional jump from T5 to T2, one would simply modify the microinstruction corresponding to state T5. A conditional branch field would be used to test the condition, and the address field would be set to the micro-address for state T2. This is a relatively simple change to the microcode.

Hardwired Control: This approach uses a fixed logic circuit (state machine) to generate control signals. The state transitions (e.g., T2 -> T3 -> T4) are typically managed by a sequence counter or a set of flip-flops with hardwired transition logic. Adding a non-sequential jump from T5 back to T2 requires adding new combinational logic gates that detect the specific condition at T5 and override the normal operation of the sequence counter to force-load the state representing T2. This is a significant and complex modification to the physical circuitry.

During the instruction fetch phase:

1. The address of the instruction is in the Program Counter (PC).
2. The content of the PC is copied to the Memory Address Register (MAR): MAR <- PC.
3. The control unit sends a 'read' signal to memory.
4. Memory places the instruction word at the address specified by the MAR onto the data bus.
5. The Memory Buffer Register (MBR), also known as the Memory Data Register (MDR), receives this instruction word from the data bus.
6. The content of the MBR is then copied to the Instruction Register (IR): IR <- MBR.
   Therefore, the MBR's key function in this phase is to act as a temporary holding register for the instruction coming from memory.