Unit1 - Subjective Questions

An Instruction Code is a group of bits that instructs the computer to perform a specific operation. It is the most basic command that the hardware can execute.

Basic Instruction Format

The basic computer has a 16-bit instruction register (IR). The instruction format is divided into three parts:

1. Addressing Mode (I-bit):

   • Located at bit 15.
   • If , it is Direct Addressing.
   • If , it is Indirect Addressing.

2. Opcode (Operation Code):

   • Located at bits 12 through 14 (3 bits).
   • It specifies the operation to be performed (e.g., ADD, MOV, LOAD).
   • Since it is 3 bits, it can define up to distinct operations.

3. Address:

   • Located at bits 0 through 11 (12 bits).
   • This field specifies the memory address of the operand.

A basic computer uses several registers to handle data and memory addresses efficiently. Below is the list of essential registers:

The Common Bus System is a shared pathway that connects all registers and memory in a computer to facilitate efficient data transfer. Instead of having wires connecting every register to every other register (which is complex and expensive), a common bus allows only one transfer at a time.

Architecture Highlights

1. Multiplexers: The bus is typically constructed using multiplexers (MUX). For a system with 8 registers, a set of multiplexers is used to select which register's data goes onto the bus.
2. Selection Lines (): Three selection lines control the multiplexers to choose the source of the data.
   • For example, if , the contents of register AR might be placed on the bus.
3. Bus to Destination: The data on the bus is available to all registers. To transfer data from the bus to a specific register, the Load (LD) input of the destination register must be enabled.

Summary of Transfer

• Source Selection: Controlled by MUX Select lines.
• Destination Selection: Controlled by the Load signal of the receiving register.
• Memory: Memory Read/Write operations are also connected to this bus.

The addressing mode determines how the address field of an instruction is interpreted to find the Effective Address (EA) of the operand.

1. Direct Addressing ()

• The address part of the instruction contains the actual address of the operand.
• Effective Address (EA) = Address field of instruction.
• Example: If the instruction is ADD 450 and , the operand is found exactly at memory location 450.

2. Indirect Addressing ()

• The address part of the instruction contains an address where the actual address of the operand is stored (a pointer).
• Effective Address (EA) = Memory[Address field].
• Example: If the instruction is ADD 450 and :
  1. Go to memory location 450.
  2. Read the content found there (e.g., 700).
  3. The actual operand is at location 700.

Comparison

Computer instructions are binary codes that tell the computer to perform specific micro-operations. In a basic computer, these are categorized into three types based on the Opcode (bits 12-14) and the Mode bit (bit 15).

1. Memory Reference Instructions (MRI)

• Opcode: 000 to 110 (binary).
• Purpose: These instructions refer to a specific memory address for operands.
• Format: (1 bit) + Opcode (3 bits) + Address (12 bits).
• Examples: AND, ADD, LDA, STA.

2. Register Reference Instructions (RRI)

• Opcode: 111 (binary) with (Bit 15 is 0).
• Purpose: Perform operations on the AC register or flags. No memory address is needed.
• Format: 0111 (Fixed 4 bits) + Register Operation (12 bits).
• Examples: CLA (Clear AC), CMA (Complement AC).

3. Input-Output Instructions (IOI)

• Opcode: 111 (binary) with (Bit 15 is 1).
• Purpose: Communicate with input/output devices.
• Format: 1111 (Fixed 4 bits) + I/O Operation (12 bits).
• Examples: INP (Input char), OUT (Output char), ION (Interrupt On).

The Timing and Control unit ensures that operations in the computer occur in the correct sequence and at the right time.

Components

1. Instruction Register (IR): Bits 12-14 are decoded by a decoder into signals through . Bit 15 determines the addressing mode ().
2. Control Logic Gates: Combine decoder outputs, timing signals, and other flags to generate control signals for specific micro-operations.
3. Clock: A master clock generator provides continuous pulses.

Sequence Counter (SC)

• The SC is a 4-bit binary counter.
• It is connected to a decoder to produce timing signals .
• Function: The SC counts from 0 to 15. Each count activates a specific timing signal .
• Reset: The SC is usually cleared to 0 (reset) at the end of an instruction execution (e.g., ), allowing the cycle to restart for the next instruction.

The Instruction Cycle consists of the steps the computer takes to process a single instruction. It generally consists of the following phases:

Phases

1. Fetch: Read the instruction from memory.
2. Decode: Decode the instruction to determine the operation and the effective address.
3. Execute: Perform the operation.
4. Interrupt Check: Check if an interrupt is pending (optional/advanced step).

Flowchart Description

1. Start ().
2. Fetch ():
   • : Transfer PC to AR ().
   • : Read Memory at AR into IR (), Increment PC ().
3. Decode ():
   • Decode Opcode ().
   • Inspect bit 15 ().
   • Transfer address part of IR to AR ().
4. Decision Point:
   • If and : Execute Register Reference Instruction ().
   • If and : Execute Input-Output Instruction ().
   • If $D_7
     eq 1IT_4, T_5, \dots$.
5. End: Reset to begin the next cycle.

The Fetch and Decode phases occur at the beginning of every instruction cycle, controlled by timing signals and .

Fetch Phase

1. • The address of the next instruction (held in PC) is transferred to the Address Register (AR). This is necessary because memory communicates via the AR.

2. • : The instruction at the address in AR is read from memory and placed into the Instruction Register (IR).
   • : The Program Counter is incremented to point to the next instruction.

Decode Phase

3. • The opcode part (bits 12-14) is decoded into signals through .
   • The address part (bits 0-11) is moved to AR (preparing for operand fetch if needed).
   • The mode bit (bit 15) is stored in flip-flop .

The AND instruction performs a bitwise logical AND operation between the contents of the Accumulator (AC) and the memory word specified by the effective address.

Logic

1. The instruction is fetched and decoded.
2. Control determines it is a Memory Reference Instruction ( is active).
3. The operand is read from memory.
4. The logic operation is performed.

RTL Execution

Assuming the fetch and decode phases () are complete:

• • Read the operand from memory (address in AR) into the Data Register (DR).

• • Perform bitwise AND between AC and DR.
  • Store the result in AC.
  • Reset Sequence Counter () to 0 to end the instruction cycle.

BSA stands for Branch and Save Return Address. It is used to implement subroutines (function calls). It saves the address of the next instruction (return address) and jumps to a new location to execute a sub-program.

Mechanism

When BSA <address> is executed:

1. The current value of the PC (which points to the next instruction) is stored at the memory location specified by the <address>.
2. The PC is updated to point to <address> + 1, which is the beginning of the subroutine code.

RTL Execution ()

Assuming Fetch/Decode is done:

• • Save the current PC (return address) into the memory location pointed to by AR.
  • Increment AR to point to the first instruction of the subroutine.

• • Transfer the address of the subroutine's first instruction into the PC.
  • Reset SC to start executing the subroutine.

ISZ stands for Increment and Skip if Zero. It is a Memory Reference Instruction used primarily for implementing loop counters.

Operation

1. It reads the word at the specified memory address.
2. It increments the value by 1.
3. It writes the value back to memory.
4. If the result of the increment is Zero, the Program Counter (PC) is incremented (skipping the next instruction).

RTL Execution ()

• (Read data).
• (Increment data).
• .

Utility in Loops

A common pattern is to set a memory location to a negative number (e.g., -10). The loop body executes, and at the end, ISZ is called on that location. It increments to -9, -8... until it hits 0. When it hits 0, it skips the "Branch Back" instruction, effectively terminating the loop.

The Input-Output configuration handles the transfer of data between the computer and external devices (keyboard, printer, etc.). Since I/O devices are much slower than the CPU, a synchronization mechanism is required.

Components

1. Input Register (INPR): 8-bit register holding input character.
2. Output Register (OUTR): 8-bit register holding output character.
3. FGI (Input Flag): A 1-bit flip-flop.
   • Set (1): New information is available in INPR (CPU can read).
   • Clear (0): INPR is empty or data has been accepted by CPU.
4. FGO (Output Flag): A 1-bit flip-flop.
   • Set (1): OUTR is free/ready to receive new data from the CPU.
   • Clear (0): OUTR is currently printing/processing data.

Handshaking Process

• Input: The interface sets FGI to 1 when a key is pressed. The CPU checks FGI; if 1, it reads INPR into AC and clears FGI to 0.
• Output: The CPU checks FGO; if 1, it transfers data from AC to OUTR and clears FGO to 0. The device sets FGO back to 1 when printing is done.

The Interrupt Cycle allows the computer to respond to external events (like I/O requests) immediately, interrupting the current program flow.

Interrupt Enable (IEN) and R Flip-Flop

• IEN: Used to enable or disable interrupts.
• R Flip-Flop: Used to distinguish between a normal instruction cycle () and an interrupt cycle ().

Transition Logic

At the end of the Execute phase (usually ends), the control checks:

The Interrupt Cycle (When )

Instead of fetching a new instruction, the computer executes the interrupt cycle:

1. • Prepare to save the return address. Interrupt vectors usually start at address 0.
2. • Store the current PC (Return Address) at memory location 0.
   • Clear PC.
3. • Increment PC to 1 (Start of Interrupt Service Routine).
   • Disable further interrupts (IEN=0).
   • Reset R and SC to resume normal Fetch cycle for the ISR instructions.

The Little Man Computer (LMC) is an instructional model of a computer, created by Dr. Stuart Madnick in 1965. It simplifies the complex Von Neumann architecture into a scenario involving a 'Little Man' working in a mailroom.

Architecture Metaphor

1. The Little Man (Control Unit & ALU): He performs the actions (reading, calculating, moving data).
2. Mailboxes (Memory): There are usually 100 mailboxes (numbered 00 to 99). Each can hold a 3-digit number (instruction or data).
3. Calculator (Accumulator): A device used by the Little Man to perform addition and subtraction. It holds the temporary result.
4. Hand Counter (Program Counter): Tells the Little Man which mailbox number to visit next to get an instruction.
5. In Basket (Input): Where the user submits numbers.
6. Out Basket (Output): Where the Little Man places results.

Significance

It effectively teaches the Fetch-Decode-Execute cycle without the complexity of binary, bus systems, or digital logic gates.

The LMC uses a simplified decimal instruction set. A 3-digit number in a mailbox represents an instruction (1st digit is Opcode, next 2 are Address).

1. ADD (1xx):

   • Add the contents of mailbox xx to the value currently in the Calculator (Accumulator).
   • Example: 150 adds value at mailbox 50 to the Calculator.

2. SUB (2xx):

   • Subtract the contents of mailbox xx from the Calculator value.
   • Example: 250 subtracts value at mailbox 50 from Calculator.

3. STA (3xx) - Store:

   • Store the value from the Calculator into mailbox xx. This is a destructive write.
   • Example: 399 saves the result into mailbox 99.

4. LDA (5xx) - Load:

   • Load the value from mailbox xx into the Calculator. The previous calculator value is overwritten.
   • Example: 510 loads the value from mailbox 10.

5. BRA (6xx) - Branch Always:

   • Set the Hand Counter (Program Counter) to xx. The next instruction will be fetched from that address.
   • Example: 600 jumps the program back to mailbox 00.

The control unit can be designed in two major ways:

Hardwired Control

• Logic: Uses fixed logic circuits (gates, flip-flops, decoders).
• Design: The control logic is physically wired onto the chip.
• Speed: Faster, as it generates control signals directly through combinational logic.
• Flexibility: Difficult to modify. Changing the instruction set requires rewiring the hardware.
• Complexity: Becomes very complex (RISC style) as the number of instructions increases.

Microprogrammed Control

• Logic: Uses a control memory (ROM) to store micro-instructions.
• Design: Control signals are generated by reading a sequence of micro-instructions from control memory.
• Speed: Generally slower due to memory access time for control store.
• Flexibility: Flexible. New instructions can be added by updating the microcode (firmware) without changing hardware.
• Complexity: Easier to design and manage for complex instruction sets (CISC style).

BUN (Branch Unconditionally) is a Memory Reference Instruction that alters the sequence of program execution.

Function

It transfers the program control to the instruction located at the effective address specified in the instruction. It is essentially a "JUMP" command.

RTL Execution ()

Assuming Fetch/Decode complete:

• • The address in the Address Register (AR), which is the effective address, is copied directly into the Program Counter (PC).
  • The next fetch cycle will read the instruction from this new address.

Difference from BSA

• BUN: Just jumps. It does not save the return address. It is a one-way trip.
• BSA: Saves the current PC (Return Address) before jumping, allowing the program to return later (used for subroutines).

The Accumulator (AC) is the main processing register. Its operations are controlled by specific control signals derived from the instruction decoder and timing signals.

Major Control Functions

We can express the control inputs (Load, Increment, Clear) as boolean functions of the control variables (, etc.).

1. LD (Load AC):

   • AC is loaded from Memory (AND, ADD, LDA) or from DR.
   • Example for AND:
   • Example for ADD:
   • Example for LDA:
   • Example for INP: (where )

2. CLR (Clear AC):

   • AC is cleared usually by the CLA instruction.
   • (where , Register Reference).

3. INR (Increment AC):

   • Increment AC usually by the INC instruction.

Summary Equation

The complete control gate logic is the sum of all these conditions. For example:

Register Reference Instructions are recognized when the Opcode is $111$ () and the Mode bit is $0$ ().

Format

• Bits 15-12: 0111
• Bits 11-0: Specify the specific register operation. Only one bit is usually set to 1 in this field to specify the operation.

Execution Timing

These are executed during timing signal . ().

Examples

1. CLA (Clear Accumulator):

   • Hex Code: 7800
   • RTL:
   • Bit 11 is set.

2. CMA (Complement Accumulator):

   • Hex Code: 7200
   • RTL: (1's complement).
   • Bit 9 is set.

3. HLT (Halt):

   • Hex Code: 7001
   • RTL: (Stops the start-stop flip-flop).
   • Bit 0 is set.

The Memory Unit stores instructions and data. In the common bus system, it acts as both a source and a destination for data.

Connection to Bus

• Address Input: Connected to the Address Register (AR). The memory always reads/writes at the location specified by AR.
• Data Output: Connected to the Bus. When 'Read' is active, memory places data onto the bus.
• Data Input: Receives data from the Bus (specifically from a register driving the bus) when 'Write' is active.

Control Signals

1. Read Operation:
   • Activated when the Read control input of the memory is enabled.
   • The content of the address specified by AR is placed onto the bus.
   • Example: Fetching an instruction ().
2. Write Operation:
   • Activated when the Write control input is enabled.
   • Data currently on the bus is written into the memory address specified by AR.
   • Example: STA instruction (Store Accumulator).