Unit 3: Field Effect Transistor (FET)

I. Orientation: The Field Effect Principle

The FET is a three-terminal, unipolar semiconductor device in which output current is controlled by the transverse electric field of a reverse-biased or insulated gate, not by a forward-biased junction. Conduction relies on majority carriers only, distinguishing it from the bipolar transistor.

• Terminals: Source (S), where majority carriers enter; Drain (D), where they leave; Gate (G), the control electrode.
• Channel: the conducting path between source and drain; n-channel carries electrons, p-channel carries holes.
• Unipolar operation: current is carried by one carrier type only (electrons in n-channel), so there is no minority-carrier storage.
• Voltage control: the gate voltage V_GS sets the drain current I_D; ideally the gate draws negligible current.
• High input impedance: the reverse-biased or oxide-insulated gate gives input resistance of 10⁸–10¹⁵ Ω, versus a few kΩ for a BJT base.
• Square-law behaviour: in saturation, I_D varies with the square of gate overdrive, unlike the exponential I_C–V_BE law of the BJT.

II. Junction Field Effect Transistor (JFET)

The JFET controls channel width by reverse-biasing a p–n junction gate.

A. Structure and working of JFET

A JFET is a bar of doped silicon with a reverse-biased gate junction squeezing the channel.

• Construction: an n-type channel (n-channel JFET) with ohmic drain and source contacts; two heavily-doped p⁺ gate regions diffused on either side and joined internally.
• Depletion control: the gate–channel junction is always reverse biased (V_GS ≤ 0 for n-channel), so gate current ≈ 0 and a depletion region intrudes into the channel.
• Working — ohmic region: for small V_DS with V_GS = 0, the channel acts as a resistor and I_D rises almost linearly with V_DS.
• Working — pinch-off: as V_DS increases, the reverse bias near the drain widens, the depletion layers meet, and the channel "pinches off"; I_D saturates at I_DSS (drain current at V_GS = 0).
• Gate control: making V_GS more negative widens the depletion region for all V_DS, reducing channel width and I_D.
• Pinch-off voltage V_P: the V_GS at which the channel is fully depleted and I_D → 0.

Shockley equation (saturation):
  I_D = I_DSS (1 − V_GS/V_P)^2

• I_D: drain current; I_DSS: saturation current at V_GS = 0; V_GS: gate–source voltage; V_P: pinch-off (gate cut-off) voltage.

III. Metal-Oxide-Semiconductor FET (MOSFET)

The MOSFET replaces the junction gate with a metal (or poly) electrode insulated by a thin SiO₂ layer, giving even higher input impedance.

A. Structure and working of MOSFET

The insulated gate modulates channel charge capacitively rather than through a junction.

• Common structure: p-type substrate with two n⁺ regions (source, drain); a thin SiO₂ layer (a few nm) under a metal gate forms a capacitor over the region between them.
• Threshold voltage V_T: the minimum V_GS that inverts the surface into a conducting channel.

1. Enhancement-type (E-MOSFET):

• No built-in channel: with V_GS = 0 no channel exists, so I_D = 0 (normally-off).
• Inversion: raising V_GS above V_T attracts electrons to the surface, forming an induced n-channel; higher V_GS enhances conduction.
• Saturation law: governed by gate overdrive above threshold.

E-MOSFET (saturation):
  I_D = k (V_GS − V_T)^2

• k: conduction parameter (A/V²) set by device geometry and process; V_T: threshold voltage.

2. Depletion-type (D-MOSFET):

• Built-in channel: a physical channel is diffused, so current flows at V_GS = 0 (normally-on).
• Both polarities: negative V_GS depletes the channel (like a JFET); positive V_GS enhances it, so it works in either mode.

IV. Output and Transfer Characteristics

These two curve families fully describe FET behaviour.

A. Output characteristics

The output (drain) characteristic plots I_D against V_DS at fixed V_GS.

• Ohmic (triode) region: for small V_DS the device behaves resistively; I_D rises steeply and nearly linearly with V_DS.
• Pinch-off point: occurs where V_DS = V_GS − V_P (JFET) or V_DS = V_GS − V_T (MOSFET); beyond it the channel is pinched at the drain end.
• Saturation (active) region: I_D stays almost constant as V_DS increases; each higher (less negative) V_GS gives a higher saturation current.
• Breakdown region: at large V_DS the drain junction breaks down and I_D shoots up — the safe operating limit.

B. Transfer characteristics

The transfer characteristic plots I_D against V_GS at a fixed V_DS in saturation.

• JFET / D-MOSFET: a parabola from (V_P, 0) to (0, I_DSS) following the Shockley square law; conduction exists at V_GS = 0.
• E-MOSFET: I_D stays zero until V_GS = V_T, then rises as (V_GS − V_T)².
• Worked example: JFET with I_DSS = 8 mA, V_P = −4 V, at V_GS = −2 V:
  
  TEXT

  I_D = 8 mA × (1 − (−2)/(−4))^2
      = 8 mA × (1 − 0.5)^2 = 8 × 0.25 = 2 mA

V. FET Parameters

Small-signal parameters link the three curve families and set amplifier performance.

A. Transconductance (g_m)

Transconductance measures how effectively V_GS controls I_D.

• Definition: the slope of the transfer curve at constant V_DS.
  
  TEXT

  g_m = ∂I_D/∂V_GS  |_(V_DS const)
  g_m = g_m0 (1 − V_GS/V_P),  g_m0 = −2 I_DSS/V_P

• g_m0: transconductance at V_GS = 0; typical values 1–10 mS. Units: siemens (mA/V).

B. Drain (output) resistance and amplification factor

These describe the drain side and overall gain capability.

• Drain resistance r_d: the reciprocal slope of the output curve in saturation, r_d = ∂V_DS/∂I_D at constant V_GS; typically tens of kΩ to MΩ.
• Amplification factor μ: the intrinsic voltage gain, tying the two together.
  
  TEXT

  μ = ∂V_DS/∂V_GS |_(I_D const) = g_m × r_d

• Input resistance: very high (10⁸ Ω JFET, up to 10¹⁵ Ω MOSFET) because the gate draws almost no current.

VI. Applications of the FET

The FET's voltage-controlled channel supports both linear and switching uses.

A. Application of FET as a voltage variable resistor (VVR)

In the deep ohmic region the FET acts as a resistor whose value is set by V_GS.

• Operating region: hold V_DS small (near zero) so the channel behaves linearly and no saturation occurs.
• Control law: the drain–source resistance r_DS rises as V_GS moves toward pinch-off, narrowing the channel.
  
  TEXT

  r_DS = r_DS(on) / (1 − V_GS/V_P)

• r_DS(on): minimum on-resistance at V_GS = 0; increasing |V_GS| increases r_DS smoothly.
• Uses: automatic gain control, electronically-tunable attenuators, and voltage-controlled filters where a gate voltage replaces a mechanical potentiometer.

B. MOSFET as a switch

Driven between cut-off and full conduction, the E-MOSFET is an efficient on/off switch.

1. OFF state:

• Condition: V_GS < V_T, so no channel forms and I_D ≈ 0.
• Output: the drain sits near the supply V_DD (logic HIGH); the device blocks current with only tiny leakage.

2. ON state:

• Condition: V_GS ≫ V_T drives the device into the ohmic region with a low r_DS(on) (fractions of an ohm in power devices).
• Output: V_DS ≈ I_D × r_DS(on) ≈ 0, giving logic LOW and minimal power loss.
• Advantages as a switch: near-zero gate current (voltage drive), fast switching from no minority-carrier storage, and low on-state dissipation — the basis of CMOS logic and power converters.

VII. Advantages of FET over Transistor

The FET's construction gives distinct edges over the BJT for many applications.

• High input impedance: the reverse-biased or insulated gate gives 10⁸–10¹⁵ Ω versus a few kΩ for the BJT, so the FET loads the source lightly.
• Voltage-controlled: it is driven by V_GS with negligible gate current, whereas the BJT needs continuous base current I_B.
• Unipolar / no minority carriers: absence of minority-carrier storage gives faster switching and lower charge-storage delay.
• Low noise: without junction recombination on the input side, the FET generates less noise, suiting front-end amplifiers.
• Thermal stability: I_D has a negative temperature coefficient, so the channel resists thermal runaway rather than promoting it like the BJT.
• Smaller and simpler fabrication: MOSFETs occupy less chip area and need fewer steps, enabling very high integration density in ICs.
• Good isolation: the tiny gate current isolates input from output, easing cascading of stages.