Unit 2: Bipolar Junction Transistor (BJT)

The bipolar junction transistor (Shockley, Bardeen and Brattain, Bell Labs, 1947–1948) is a three-terminal current-controlled device built from two back-to-back PN junctions sharing a common central region. Its action depends on the injection of minority carriers across a forward-biased junction and their collection across a reverse-biased one, giving current and power gain.

• Three regions: emitter (heavily doped), base (thin, lightly doped, ~1 µm), collector (moderately doped, largest area for heat dissipation).
• Two junctions: emitter–base junction (JE) and collector–base junction (JC).
• Both carriers conduct: electrons and holes both take part — hence "bipolar."
• Base transport requirement: the base must be thinner than the minority-carrier diffusion length so most injected carriers reach the collector.
• Governing gains: α = I_C/I_E (0.95–0.995) and β = I_C/I_B (typically 50–300).

II. Transistor Structure and Current Flow

How the two-junction sandwich carries current.

A. PNP and NPN transistors

The two polarity types are structural mirror images that differ in doping order and biasing sign.

• NPN: N-emitter, P-base, N-collector; majority injected carriers are electrons. Conventional current enters at collector and base, exits at emitter.
• PNP: P-emitter, N-base, P-collector; injected carriers are holes. Conventional current enters at emitter, exits at collector and base.
• Biasing rule for active mode: JE forward-biased, JC reverse-biased.
  • NPN: V_BE ≈ +0.7 V, V_CB > 0.
  • PNP: V_EB ≈ +0.7 V, V_BC > 0.
• Preference: NPN is favoured because electron mobility exceeds hole mobility, giving faster switching and higher f_T.

B. Current components in BJT

Emitter current splits into useful collected current and unavoidable loss currents.

• Emitter current: I_E = I_nE + I_pE, where I_nE is injected majority carriers and I_pE is the reverse hole injection into the emitter (a loss).
• Recombination in base: a small fraction of injected carriers recombine, supplying most of I_B.
• Collector current: I_C = I_nC + I_CBO, where I_CBO is the reverse saturation (leakage) current with emitter open.
• Fundamental relation:

I_E = I_C + I_B
I_C = α·I_E + I_CBO

• Emitter injection efficiency (γ): ratio of useful injected current to total emitter current; near 1 for a heavily doped emitter.
• *Base transport factor (β):* fraction of injected carriers reaching the collector; α = γ·β.

III. Static Characteristics

The DC voltage–current curves that fix the operating point.

A. BJT static characteristics (Input and Output)

Static characteristics plot terminal currents against terminal voltages with a chosen quantity held constant, shown here for CE.

• Input characteristic: I_B versus V_BE at constant V_CE.
  • Resembles a forward-biased diode; conduction begins near V_BE ≈ 0.5–0.7 V (Si).
  • Higher V_CE shifts the curve slightly right (base width narrowing).
• Output characteristic: I_C versus V_CE at constant I_B.
  • Nearly horizontal lines in the active region; I_C set by I_B, almost independent of V_CE.
  • Family of curves, one per I_B step.
• Key slopes give h-parameters: input slope → h_ie, output slope → h_oe.

B. Early effect

The Early effect is the modulation of effective base width by the collector–base reverse voltage.

• Mechanism: increasing V_CB widens the JC depletion layer, thinning the neutral base.
• Consequences: less base recombination → α and β rise slightly, and I_C increases gently with V_CE (finite output slope).
• Early voltage (V_A): extrapolated output lines meet the V_CE-axis at −V_A (typically 50–150 V).

r_o = V_A / I_C     (output resistance from Early effect)

• Extreme case: at very high V_CB the base can vanish — punch-through breakdown.

IV. Transistor Configurations and Operating Regions

The three ways of connecting the device and the three modes it can occupy.

A. CB, CC, CE configurations

Each configuration designates which terminal is common to input and output, fixing the gain profile.

• Common Base (CB): input at emitter, output at collector, base common.
  • Current gain α < 1; high voltage gain; low input resistance (~20 Ω), high output resistance.
  • Best for high-frequency and impedance-matching stages.
• Common Emitter (CE): input at base, output at collector, emitter common.
  • Current gain β; both voltage and current gain high → highest power gain; 180° phase inversion.
  • Moderate input (~1 kΩ) and output (~40 kΩ) resistance; the workhorse amplifier.
• Common Collector (CC): input at base, output at emitter, collector common (emitter follower).
  • Voltage gain ≈ 1; high current gain; high input, low output resistance → buffer/impedance matcher.

β = α / (1 − α)        α = β / (1 + β)

B. Cut off, active, and saturation regions

The junction bias states define three regions on the output plane.

• Cut-off: both junctions reverse-biased; I_C ≈ I_CEO ≈ 0; transistor acts as an open switch.
• Active: JE forward, JC reverse; I_C = β·I_B; linear amplification region.
• Saturation: both junctions forward-biased; V_CE small (V_CE(sat) ≈ 0.2 V); I_C limited by external circuit, not β; acts as a closed switch.
• Switching pair: cut-off (logic 0) and saturation (logic 1) form the two states in digital use.

V. Small-Signal Modelling of the CE Stage

Replacing the nonlinear device with a linear two-port for AC analysis.

A. CE configuration as two port network

A biased transistor is treated as a linear two-port relating small-signal input and output quantities about the Q-point.

• Port variables: input (V_1 = v_be, I_1 = i_b), output (V_2 = v_ce, I_2 = i_c).
• Chosen independent variables for h-model: input current I_1 and output voltage V_2, because a BJT is naturally current-driven at the input and voltage-driven at the output.
• Defining equations:

V_1 = h_i·I_1 + h_r·V_2
I_2 = h_f·I_1 + h_o·V_2

B. h parameters

The hybrid parameters are the four coefficients of the two-port equations, so named because they mix impedance, admittance and dimensionless ratios.

• h_i (input impedance): V_1/I_1 with V_2 = 0 (output shorted); ohms.
• h_r (reverse voltage ratio): V_1/V_2 with I_1 = 0 (input open); dimensionless, very small.
• h_f (forward current gain): I_2/I_1 with V_2 = 0; dimensionless, ≈ β for CE.
• h_o (output admittance): I_2/V_2 with I_1 = 0; siemens.
• CE subscripts: h_ie, h_re, h_fe, h_oe. Typical: h_ie ≈ 1–2 kΩ, h_fe ≈ 100, h_re ≈ 2.5×10⁻⁴, h_oe ≈ 25 µS.

C. h parameter equivalent circuit

The four parameters map onto a fixed circuit topology valid for any configuration.

• Input loop: a series resistance h_i with a dependent voltage source h_r·V_2.
• Output loop: a dependent current source h_f·I_1 in parallel with conductance h_o.
• Small-signal gains (load R_L):

A_i = −h_f / (1 + h_o·R_L)
R_in = h_i + h_r·A_i·R_L
A_v = A_i·R_L / R_in

• Simplification: for low-frequency work h_r and h_o are often neglected, giving A_i ≈ −h_fe and R_in ≈ h_ie.

VI. Biasing, Load Line and Datasheets

Setting and reading the operating point in practice.

A. Biasing and load line analysis

Biasing establishes a stable DC Q-point in the active region; the load line shows the constraint the external circuit imposes.

• Purpose: keep the transistor in the active region so the signal swings without clipping or cut-off.
• DC load line: from the collector loop V_CC = I_C·R_C + V_CE.
  • Endpoints: saturation (V_CE = 0, I_C = V_CC/R_C) and cut-off (I_C = 0, V_CE = V_CC).
• Q-point: intersection of the load line with the chosen I_B output curve; place near the centre for maximum swing.
• Common schemes:
  1. Fixed bias: single base resistor; simple but Q-point drifts strongly with β and temperature (poor stability factor S ≈ 1+β).
  2. Voltage-divider bias: R_1–R_2 divider plus emitter resistor R_E; β-independent, low S — the standard stable design.
• Stabilisation: R_E provides negative feedback; rising I_C raises V_E, lowering V_BE and countering the increase.

Voltage-divider Q-point:
V_B = V_CC·R_2/(R_1+R_2)
I_C ≈ (V_B − V_BE)/R_E

B. Understanding datasheets of BJTs

A datasheet states the safe limits and typical parameters needed to choose and bias a device.

• Absolute maximum ratings: V_CEO (collector–emitter breakdown), V_CBO, V_EBO, I_C(max), and P_D(max) power dissipation — never to be exceeded.
• DC parameters: h_FE (DC current gain, given as a range), V_CE(sat), V_BE(on), I_CBO leakage.
• AC/small-signal parameters: h_fe, transition frequency f_T (gain-bandwidth), C_ob (output capacitance).
• Thermal data: junction-to-ambient resistance θ_JA (°C/W) for computing rise: T_J = T_A + P_D·θ_JA.
• Derating and SOA: the safe operating area curve bounds simultaneous V_CE and I_C; power ratings derate above 25 °C.
• Worked read: a 2N2222 lists V_CEO = 40 V, I_C = 800 mA, P_D = 500 mW, h_FE = 100–300, f_T = 300 MHz — enough to fix R_C for a target I_C while staying inside all limits.