Unit 5 - Practice Quiz

For sustained oscillation, the signal fed back to the input must be in phase with the original input signal. A 360-degree (or 0-degree) phase shift ensures this positive feedback condition is met.

For stable, sustained oscillations, the loop gain magnitude must be exactly one. If , the oscillations grow until the amplifier saturates. If , the oscillations die out.

The name "RC phase shift oscillator" comes directly from its feedback network, which consists of a series of Resistor-Capacitor (RC) stages to produce the necessary phase shift.

An inverting amplifier provides a 180° phase shift. The feedback network must provide the remaining 180° for oscillation. This is typically achieved using three RC stages, with each stage contributing approximately 60° of phase shift.

The Wien-bridge oscillator is widely used in applications like audio generators because it is capable of producing a very clean, high-quality sine wave with minimal distortion.

Since a non-inverting amplifier has a 0° phase shift, the feedback network must also provide a 0° phase shift to meet the Barkhausen criterion. The Wien-bridge network is designed to have zero phase shift at exactly one frequency.

The defining feature of a Hartley oscillator is its tank circuit, which uses two inductors (or a single tapped inductor) in parallel with a single capacitor to create resonance.

A Colpitts oscillator is the dual of a Hartley oscillator. Its tank circuit consists of a single inductor in parallel with two capacitors in series (forming a tapped capacitor arrangement).

Both oscillators use an Inductor (L) and a Capacitor (C) to form a resonant tank circuit that determines the oscillation frequency, hence they are known as LC oscillators.

The versatile 555 timer IC is packaged in a standard 8-pin Dual In-line Package (DIP).

The 555 timer is most commonly configured to operate in either monostable mode (to create a single timed pulse) or astable mode (to create a continuous series of pulses).

The RESET pin (Pin 4) is an active-low input. When a low voltage is applied to this pin, it forces the timer's output to go low, regardless of the state of the other inputs.

An astable multivibrator has no stable states. It continuously switches back and forth between two unstable states, making it a free-running oscillator.

It's called a 'one-shot' because it has one stable state. When triggered, it produces a single output pulse of a specific duration before returning to its stable state.

Because an astable multivibrator continuously alternates between its two unstable (high and low) states, it produces a periodic square or rectangular pulse train.

The defining characteristic of a VCO is that its output oscillation frequency is directly controlled by an analog input voltage.

A PLL works by using a VCO to generate a frequency that is locked to the phase of an input signal. The VCO's frequency is adjusted based on the output of a phase detector.

A basic PLL system consists of a phase detector to compare input and feedback frequencies, a low-pass filter to smooth the detector's output, and a voltage-controlled oscillator (VCO) that generates the output frequency.

The oscillation frequency is the frequency at which the RC network produces the required 180° phase shift. This frequency is directly dependent on the R and C values used in the feedback stages.

At the resonant frequency, the Wien-bridge feedback network attenuates the signal by a factor of 1/3. To satisfy the Barkhausen criterion of loop gain , the non-inverting amplifier must have a gain (A) of exactly 3.

According to the Barkhausen criterion, for sustained oscillations, the loop gain must be equal to 1, and the total phase shift around the loop must be 0° or 360°. The amplifier has a gain of -50, which means its magnitude is and it introduces a 180° phase shift (inverting amplifier). To make the total phase shift 360°, the feedback network must introduce another 180° shift. To make the loop gain magnitude 1, , so , which means .

The Barkhausen criterion defines the condition for steady-state oscillation. However, to start the oscillation, the amplitude must grow from the initial electronic noise present in the circuit. By making the loop gain slightly greater than 1, the amplitude of the signal is guaranteed to increase until it is limited by the non-linearities of the active device (like saturation), at which point the effective gain reduces and the loop gain settles to 1 for a stable output.

For a three-section RC phase-shift oscillator, the frequency of oscillation is given by the formula . Plugging in the values: or 6.5 kHz.

For a BJT-based RC phase-shift oscillator, the feedback network has an attenuation factor and also loads the amplifier's output. The analysis shows that for the loop gain to be at least 1, the transistor's current gain () must be greater than . The theoretical minimum value occurs under specific loading conditions and is greater than 44.5. A gain of 29 is the requirement for an ideal op-amp based oscillator, which doesn't have the same loading effects as a BJT amplifier.

In a Wien-bridge oscillator, the lead-lag network provides zero phase shift at the resonant frequency and has an attenuation factor () of 1/3. The non-inverting amplifier's gain is given by . For sustained oscillations, the loop gain must be at least 1. Therefore, , which means . So, , which implies . To ensure the oscillations start, the gain must be slightly greater than 3, so the ratio must be slightly greater than 2.

The Wien-bridge oscillator is known for its high-quality, low-distortion sinusoidal output, especially when an amplitude stabilization mechanism (like using diodes or a JFET) is included. This makes it ideal for audio testing and calibration applications where a pure sine wave is required. While simple, other oscillators can be simpler, and it is not suitable for very high frequencies.

In a Hartley oscillator's tank circuit, the total inductance is the sum of the individual inductances plus twice the mutual inductance, assuming the coils are series-aiding. The formula is . Substituting the values: .

The feedback factor for a Colpitts oscillator is . The Barkhausen criterion requires for oscillations to start. Therefore, the minimum gain required is . Given and , the minimum gain is .

The key distinguishing feature lies in the tank circuit's feedback path. A Hartley oscillator uses an inductor that is tapped (or two separate inductors) to provide the feedback signal. A Colpitts oscillator uses a voltage divider made of two capacitors in series (a tapped capacitor arrangement) to provide the feedback signal. Both are LC oscillators and their tank circuits both provide 180° of phase shift.

The THRESHOLD pin (6) is connected to the non-inverting input of the upper comparator, which has a reference of (approx ). Since is greater than this reference, the upper comparator's output will be HIGH, which resets the internal SR flip-flop (R=1). A reset state (Q=0) causes the main output (pin 3) to go LOW. The TRIGGER pin's voltage is irrelevant in this case because the reset condition overrides the set condition.

The frequency of an astable 555 timer circuit is given by the formula . Substituting the values: . The closest answer is 1.5 kHz. (Note: using ln(2) instead of 0.693 gives a more precise )

The pulse width (T) of a 555 monostable circuit is given by . We need T = 2 seconds and C = 10 µF ( F). Rearranging the formula to solve for R: . The closest standard resistor value is 180 kΩ.

The output HIGH time () is determined by the charging path through both and . The output LOW time () is determined by the discharge path through only . Since and , the HIGH time will always be longer than the LOW time because must have a resistance greater than zero. Therefore, the duty cycle, , will always be greater than 50%.

The CONTROL pin sets the reference voltage for the upper comparator. Normally, this is . The capacitor charges towards this voltage. If this voltage is lowered to , the capacitor has to charge to a lower voltage level before the output switches. The lower comparator's reference is half of the CONTROL voltage, so it becomes . The capacitor now cycles between and . This reduced voltage swing takes less time to traverse, thus increasing the oscillation frequency.

The output frequency of a VCO is given by the formula , where is the center frequency, is the sensitivity, and is the input control voltage. Plugging in the values: .

This system describes an open-loop control scheme. A control voltage sets the VCO frequency, which in turn sets the motor voltage. There is no feedback from the actual motor speed to adjust the input control voltage. In a closed-loop system, a sensor (like a tachometer) would measure the actual motor speed, and this information would be used to correct any error in the desired speed.

The capture state (or acquisition mode) is the transitional period where the PLL detects a frequency difference between the input signal and the VCO. The phase detector produces an error voltage that is filtered and applied to the VCO, causing its frequency to sweep towards the input frequency. Once the frequencies are close enough for the loop to lock, it enters the locked state.

The phase detector is the core component that compares the phase of the incoming reference signal with the phase of the feedback signal (from the VCO). Its output is an error signal whose average DC voltage is proportional to this phase difference. This error signal is then used to control the VCO, forming the feedback mechanism that drives the loop towards a locked state.

In a locked PLL, the two inputs to the phase detector must have the same frequency. One input is the reference frequency, . The other input is the VCO output frequency divided by N, . Therefore, in the locked state, . To find the output frequency, we rearrange the formula: . With and , the output frequency is .

The 'lock range' is the range of input frequencies over which a PLL, already in lock, can remain locked. The 'capture range' is the smaller range of frequencies over which a PLL can initially achieve lock. The low-pass filter's characteristics limit the capture process, making the capture range typically narrower than the lock range. It requires a larger frequency difference to break an existing lock than it does to establish a lock in the first place.

For oscillations to start, the loop gain must be slightly greater than 1. This allows the amplitude of the oscillations to grow from the initial noise or transient signals present in the circuit. As the amplitude increases, a non-linear mechanism (like amplifier saturation or an automatic gain control circuit) reduces the effective gain until becomes exactly 1. At this point, the amplitude stabilizes, and sustained oscillation is achieved. If were exactly 1 from the start, there would be no mechanism for the oscillation to build up from an infinitesimal level.

The gain of the non-inverting op-amp is . The output amplitude stabilizes when the feedback network limits the gain. The Zener diodes will start to conduct when the voltage across reaches approximately . The voltage across is a fraction of the output voltage , determined by the voltage divider and . The voltage at the inverting input is . The voltage across is . For limiting to occur, this voltage must equal the diode clamping voltage, so . Rearranging for gives .

The final resistor of the RC network is effectively . This parallel combination is smaller than . A detailed analysis of the loaded network shows two effects: 1) The total attenuation () of the network increases because the loading reduces the voltage transfer. To overcome this higher attenuation, the amplifier's current gain () must be larger to satisfy . 2) The frequency at which the phase shift occurs is increased. The oscillation frequency for the unloaded network is . For the loaded case, the frequency becomes . Since , the denominator term increases, thus increasing the frequency.

The resonant frequency of an LC tank circuit is determined by the total equivalent inductance and capacitance. In a Hartley oscillator, the two inductors are in series from the perspective of the tank circuit. When two inductors are in series with mutual inductance , the total equivalent inductance is . The sign depends on whether the fields are aiding or opposing. In a standard Hartley configuration, the tapping point for feedback ensures the windings are connected in an aiding configuration. Therefore, the total inductance is , which leads to the modified frequency formula .

The type of a PLL is determined by the number of pure integrators in its open-loop transfer function, . Since already has a pole at the origin ( term) and the VCO is also an integrator (), a Type-II PLL has two integrators in its loop. For a system with two integrators (a Type-2 system), the steady-state error for a ramp input in frequency (which is equivalent to a parabolic input in phase, ) is a finite, constant value. The steady-state phase error is given by , where is the parabolic error constant of the loop, which is non-zero for a Type-II system. A Type-I PLL would have a ramp error, and a Type-III PLL would have zero error for this input.

The control voltage pin directly sets the voltage at the inverting input of the upper comparator (threshold) and, through an internal voltage divider, sets the voltage at the non-inverting input of the lower comparator (trigger). The upper threshold becomes , and the lower trigger level becomes . Consequently, the timing capacitor charges from to during the high period () and discharges from down to during the low period (). This allows for voltage control of the frequency and duty cycle, forming a basic VCO. The standard formulas are no longer valid.

In a Colpitts oscillator, the transistor's junction capacitances (, ) are in parallel with the tank capacitors and . Any variation in these parasitic capacitances (due to temperature or voltage changes) directly affects the resonant frequency. In the Clapp oscillator, the total tank capacitance is . If is chosen to be much smaller than and , then . The oscillation frequency becomes primarily dependent on the stable, high-Q components and . The larger capacitors and still provide the correct feedback ratio, but their variations (and the parallel parasitic capacitances) have a much smaller effect on the overall resonant frequency, thus greatly improving stability.

The relationship between frequency and control voltage is highly non-linear. The frequency is , and includes the varactor's non-linear capacitance . This results in a non-linear vs. curve. While analog techniques can provide some linearization over a small range, achieving high linearity over a wide range often requires digital pre-distortion. A microcontroller can compute the required to produce a desired linear frequency step, using the inverse of the varactor's known characteristic curve. This value is then fed to a DAC to generate the precise, non-linear control voltage needed to produce a linear change in frequency.

The operation relies on the transistors switching between cutoff and saturation. If a transistor fails to saturate due to low (), its collector-emitter voltage () during its 'on' state will be significantly higher than the typical (approx 0.2V). This affects the timing. The duration of the high state at this transistor's collector is determined by the other transistor's base timing circuit. However, the voltage to which the timing capacitor must charge/discharge is altered. Specifically, when the other transistor turns on, its base capacitor is charged through the collector resistor of the faulty BJT. Since this collector voltage is not close to 0V, the capacitor starts its charging from a higher initial voltage, meaning it takes less time to reach the turn-on voltage for the faulty BJT. This shortens the 'high' time period for the faulty transistor's collector.

An XOR phase detector produces an output whose average DC value is proportional to the phase difference. For 50% duty cycle square waves, a phase difference results in a 50% duty cycle output, which has an average voltage of . This is the center of its operating range and corresponds to the VCO's free-running frequency. Since the VCO's free-running frequency is lower than the target frequency , the control voltage fed to the VCO must be higher than the voltage that produces . For an XOR detector, a higher average voltage is produced when the output duty cycle is greater than 50%. This occurs when the phase difference is less than . A smaller phase difference means the inputs are 'different' for a larger portion of the cycle, making the XOR output high more often.

For sustained oscillation in a Wien-bridge oscillator, the gain of the non-inverting amplifier must be exactly 3. The gain is . So, we need , which means must be . The lamp will stabilize its temperature, and thus resistance, at this value. For the oscillation to start, the initial gain must be greater than 3. The cold resistance of the lamp is . The initial gain is . This is less than 3, so oscillation will not start. The question has a flaw; for this circuit to work, the positions of and should be swapped, or the lamp put in the position. However, interpreting the question as finding the required condition: to start, the initial gain must be > 3. For the amplitude to stabilize, the gain must reduce to 3. This means the resistance of the lamp must settle at . A practical circuit would arrange the components such that the cold resistance provides a gain > 3 and the hot resistance provides a gain of 3.

An ideal op-amp in an inverting configuration provides a perfect phase shift. However, a real op-amp with a finite GBWP exhibits a single-pole frequency response. Its phase shift is given by , where is the pole frequency. The open-loop gain at 10 kHz is . The required closed-loop gain is 29, which is less than 100, so it can oscillate. The op-amp contributes more than of phase shift (a phase lag). To satisfy the total phase shift condition of (or for the loop), the RC network now needs to provide less than of phase shift. An RC phase-shift network provides a smaller phase shift at a lower frequency. Therefore, the circuit will stabilize and oscillate at a frequency slightly lower than the one calculated for an ideal op-amp.

The designed pulse width of the monostable circuit is 110ms. The circuit is triggered by a 1kHz signal, which has a period of 1ms. The first falling edge of the trigger signal will start the 110ms output pulse. However, subsequent trigger pulses arrive every 1ms. A standard 555 monostable is non-retriggerable, meaning it ignores triggers while its output is high. But the key is how the trigger input is handled. The trigger input (pin 2) is level-sensitive. As long as the trigger input is held low (below ), the timer's internal flip-flop is held in the 'set' state, keeping the output high. Since the 1kHz square wave is low for 0.5ms out of every 1ms, the trigger condition is met repeatedly long before the 110ms timing cycle can complete. The capacitor never gets a chance to charge to the threshold voltage. The output will be triggered high and will remain high because it's being constantly re-asserted by the trigger pin being held low periodically.

The simple gain condition is derived assuming the transistor is an ideal current source (infinite output impedance). However, a real BJT has a finite output impedance, represented by the output admittance (). This finite impedance acts as a load on the collector and shunts the tank circuit. A more detailed analysis using the hybrid-pi model reveals that the loading effect from both the input impedance () and the output admittance () must be considered. The full condition is more complex: (where is the collector load). The term with significantly increases the required for oscillation, especially if the tank circuit impedance is high.

The condition for oscillation is that the total loop phase shift is . Let be the amplifier phase and be the feedback phase. So . If the amplifier's phase changes by a small amount due to temperature or voltage drift, the oscillation frequency must shift by to a new frequency such that the total phase is again . This means . Using a first-order approximation, . Therefore, . To minimize the frequency shift for a given amplifier phase shift , the denominator, which is the phase slope of the feedback network , must be as large as possible. This is a key principle in designing stable oscillators, and why quartz crystals, with their extremely steep phase response near resonance, are used.

When the PLL is unlocked, the input frequency and the VCO frequency are different. The phase detector output is a beat-note signal at the difference frequency, . The loop filter is a low-pass filter designed to smooth the phase detector output during lock. This filter heavily attenuates the AC beat-note signal. However, the beat note is not perfectly symmetric, so it has a small DC component. This small DC voltage is the 'pull-in' voltage that tries to slew the VCO frequency towards the input frequency. If the initial frequency difference is large, the beat-note frequency is high, and the filter attenuates it so much that the resulting DC pull-in voltage is too small to overcome the frequency difference. This filtering effect is the primary reason the capture range is smaller than the lock range. The lock range is a static DC condition where the filter's attenuation is not a factor.

While the oscillation period is fundamentally set by the RC time constants, these can be made very small by using small resistors and capacitors. However, at high frequencies, the switching speed of the transistors becomes the bottleneck. In a standard saturating astable multivibrator, the 'on' transistor is driven deep into saturation. To turn it off, the excess minority carriers stored in the base region must be removed. This process, known as storage time (), introduces a significant delay that is independent of the external RC components. This delay limits how quickly the transistor can switch off, placing an upper bound on the maximum frequency of reliable oscillation. Other factors like rise time and fall time also contribute, but storage time is often the dominant limitation in saturating logic.

The frequency is ideally . This assumes the capacitor discharge is instantaneous. In reality, the discharge occurs through a switch (e.g., a BJT or MOSFET) with a finite on-resistance, . The discharge time is roughly proportional to . At low frequencies (low ), the charging time is long, and this fixed discharge time is a negligible part of the period. At high frequencies (high ), the charging time becomes very short, comparable to the discharge time. The total period is . Since is proportional to but is constant, the total period is no longer inversely proportional to . This breaks the linear relationship between control voltage and frequency, causing the transfer function to flatten out at the high end.

To achieve a duty cycle of less than 50%, the charging time () must be made shorter than the discharging time (). In the standard circuit, the capacitor charges through and discharges through . By placing a diode in parallel with (cathode to pin 7, anode to pin 6/2), the charging path is altered. The current now flows through and the forward-biased diode, bypassing . The charging time becomes approximately . The discharge path is still through to pin 7. The discharge time remains . By choosing , we can make , resulting in a duty cycle less than 50%.

Both options A and B contribute, but A is the more fundamental electronic reason. At VHF and higher frequencies, stray and parasitic capacitances (like the transistor's junction capacitance, wiring capacitance) become significant and unpredictable. In a Colpitts oscillator, these stray capacitances appear in parallel with the main tuning capacitors and . Because and are intentionally part of the design, they can be chosen such that the stray capacitances are a small, manageable fraction of their total value. This makes the circuit's performance more predictable and stable. In a Hartley oscillator, stray capacitance across the inductor can lead to unwanted resonances and makes the circuit behavior harder to control. Furthermore, creating a precise, high-Q tapped inductor for VHF is mechanically more challenging than using two separate capacitors.