Unit 6: Introduction to Sequential Logic Circuits

1. Introduction: Combinational vs. Sequential Circuits

Sequential logic circuits are a fundamental component of digital systems. Unlike combinational circuits, their output depends not only on the present input values but also on the past sequence of inputs (i.e., the circuit's current state). This is because sequential circuits have memory elements.

• Combinational Circuits:
  • Output depends only on the current inputs.
  • No memory elements.
  • Examples: Adders, Subtractors, Multiplexers, Decoders.
• Sequential Circuits:
  • Output depends on current inputs and the previous state of the circuit.
  • Contain memory elements (latches or flip-flops).
  • Contain a feedback path from the output back to the input.
  • Examples: Flip-flops, Registers, Counters.

2. Latches (Level-Sensitive Memory)

Latches are the most basic memory elements. They are level-sensitive, meaning their output can change as long as the control signal (enable) is at a particular logic level (e.g., HIGH).

2.1 SR-Latch (Set-Reset Latch)

The SR-latch is a bistable multivibrator with two stable states. It can be built using NOR or NAND gates.

SR-Latch using NOR Gates

• Circuit: Two cross-coupled NOR gates.

• Inputs: S (Set), R (Reset).

• Outputs: Q, Q' (Q-bar, complement of Q).

• Operation:

  • Set (S=1, R=0): Sets the output Q to 1. The feedback from Q' (which becomes 0) holds Q at 1 even after S returns to 0.
  • Reset (S=0, R=1): Resets the output Q to 0. The feedback from Q (which becomes 0) holds Q' at 1, which in turn holds Q at 0 even after R returns to 0.
  • Hold/Memory (S=0, R=0): The latch maintains its previous state (Q remains unchanged). This is the memory state.
  • Invalid/Forbidden (S=1, R=1): Both Q and Q' are forced to 0. This state is avoided because if S and R go to 0 simultaneously, the final state of the latch is unpredictable (race condition).

• Truth Table (NOR Latch):

SR-Latch using NAND Gates (Active-LOW)

• Circuit: Two cross-coupled NAND gates. This is an active-LOW latch.

• Inputs: S' (Set-bar), R' (Reset-bar).

• Operation: The logic is inverted compared to the NOR latch. A LOW signal on S' sets Q=1, and a LOW signal on R' resets Q=0. The forbidden state occurs when both S' and R' are 0.

• Truth Table (NAND Latch):

2.2 D-Latch (Gated D Latch)

The D-latch (Data or Transparent Latch) solves the invalid state problem of the SR-latch. It has one data input (D) and an enable input (E or CLK).

• Circuit: An SR-latch with an additional gating network. S is connected to D, and R is connected to NOT D, through AND gates controlled by the Enable (E) signal.

• Operation:

  • When E = 1, the latch is transparent. The output Q follows the input D (Q = D).
  • When E = 0, the latch is closed. The output Q holds the last value it had just before E went LOW, regardless of any changes at the D input.

• Truth Table (D Latch):

(X = Don't Care)

3. Flip-Flops (Edge-Triggered Memory)

Flip-flops are an improvement over latches. They are edge-triggered, meaning the output changes state only at a specific point on the clock signal – either the positive edge (0 to 1 transition) or the negative edge (1 to 0 transition). This provides precise timing and avoids the transparency issue of latches.

3.1 D Flip-Flop

The D flip-flop is the simplest and most widely used flip-flop. It directly stores the value on its D input at the active clock edge.

• Logic Symbol:

• Operation: On the active clock edge (e.g., rising edge), the value at the D input is captured and transferred to the output Q. At all other times, Q remains constant. It acts as a synchronous data storage element.

• Characteristic Table:

• Characteristic Equation: Q(t+1) = D
• Excitation Table: (Shows what input D is needed to get the desired next state)

3.2 JK Flip-Flop

The JK flip-flop is the most versatile flip-flop. It has two inputs, J (like Set) and K (like Reset), and can perform Set, Reset, Hold, and Toggle operations.

• Logic Symbol:

• Operation:

  • J=0, K=0: Hold state (Q remains unchanged).
  • J=0, K=1: Reset state (Q becomes 0).
  • J=1, K=0: Set state (Q becomes 1).
  • J=1, K=1: Toggle state (Q flips to its complement, Q -> Q').

• Characteristic Table:

• Characteristic Equation: Q(t+1) = J·Q'(t) + K'·Q(t)
• Excitation Table:

Race-Around Condition: In basic level-triggered JK latches (not edge-triggered flip-flops), if J=K=1 and the clock pulse duration is longer than the propagation delay, the output Q will toggle continuously. This is the race-around condition. Edge-triggering or Master-Slave configurations solve this problem.

3.3 T Flip-Flop (Toggle Flip-Flop)

The T flip-flop has a single input, T. It is primarily used for toggling its state, making it ideal for building counters. It can be created by connecting the J and K inputs of a JK flip-flop together.

• Logic Symbol:

• Operation:

  • T=0: Hold state (Q remains unchanged).
  • T=1: Toggle state (Q flips to its complement).

• Characteristic Table:

• Characteristic Equation: Q(t+1) = T ⊕ Q(t) = T·Q'(t) + T'·Q(t)
• Excitation Table:

3.4 Master-Slave JK Flip-Flop

This configuration was designed to solve the race-around condition in JK flip-flops. It consists of two cascaded latches: a Master and a Slave.

• Circuit Structure:

  • An edge-triggered JK flip-flop acts as the Master.
  • A second SR or D latch acts as the Slave.
  • The external clock (CLK) is applied directly to the Master.
  • An inverted version of the clock (CLK') is applied to the Slave.

• Operation (Positive Edge Triggered Example):

  1. Clock is HIGH (Positive Level):
     • The Master latch is enabled and accepts inputs from J and K.
     • The Slave latch is disabled (due to the inverted clock) and holds its previous value. The external outputs (Q and Q') do not change.
  2. Clock goes LOW (Negative Edge):
     • The Master latch is disabled, locking in the state determined by J and K.
     • The Slave latch is now enabled and copies the state from the Master latch to its output. The external outputs (Q and Q') now change to reflect the new state.

This two-step process ensures that the inputs are sampled while the output is stable, and the output is updated only after the inputs have been disabled, effectively preventing the race-around condition.

4. Conversion of Basic Flip-Flops

Any flip-flop can be converted into another type by adding an appropriate combinational logic circuit at its input.

General Conversion Procedure:

1. Identify Available and Required Flip-Flops: Determine the source (available) and target (required) flip-flop types.
2. Create Excitation Tables: Write down the excitation tables for both flip-flops.
3. Form a Conversion Table: Create a table that lists the present state Q(t), the desired next state Q(t+1), the input required by the target flip-flop to achieve this transition, and the corresponding input required by the source flip-flop.
4. Derive Logic Expressions: Use K-maps to derive simplified Boolean expressions for the inputs of the source flip-flop in terms of the inputs of the target flip-flop and the present state Q(t).
5. Draw the Logic Circuit: Implement the derived expressions using logic gates and connect them to the source flip-flop to create the target flip-flop.

Example: Convert an SR Flip-Flop to a JK Flip-Flop

1. Available: SR-FF. Required: JK-FF.
2. Excitation Tables:
   • SR-FF: Requires S, R inputs.
   • JK-FF: Provides J, K inputs.
3. Conversion Table:

4. Derive Logic Expressions (using K-Maps):

   • For S:

     • K-Map inputs: J, K, Q(t)
     • Simplified Expression: S = J·Q'(t)

   • For R:

     • K-Map inputs: J, K, Q(t)
     • Simplified Expression: R = K·Q(t)

5. Draw the Logic Circuit:

5. Shift Registers

A shift register is a group of cascaded flip-flops (usually D-type) used to store and shift binary data. Each flip-flop stores one bit of data. Data can be loaded and retrieved in serial or parallel format.

5.1 Serial-In, Serial-Out (SISO)

• Operation: Data is loaded one bit at a time on each clock pulse. The stored data is also shifted out one bit at a time.
• Structure: A chain of D flip-flops where the Q output of one is connected to the D input of the next.
• Application: Used as a time-delay element. If there are N flip-flops, it takes N clock pulses for the first bit to reach the output.

5.2 Serial-In, Parallel-Out (SIPO)

• Operation: Data is loaded serially (one bit per clock pulse). After N pulses, all N bits are available simultaneously on the parallel outputs (Q0, Q1, ..., Qn-1).
• Application: Converting serial data (e.g., from a communication line) to parallel data (e.g., for a computer bus).

5.3 Parallel-In, Serial-Out (PISO)

• Operation: All data bits are loaded simultaneously in parallel using a Load/Shift control line. The data is then shifted out one bit at a time on subsequent clock pulses.
• Structure: Requires additional gating (multiplexers) to select between parallel loading and serial shifting.
• Application: Converting parallel data (from a computer bus) to serial data (for transmission).

5.4 Parallel-In, Parallel-Out (PIPO)

• Operation: All data bits are loaded simultaneously on one clock pulse and are available on the parallel outputs immediately.
• Application: Used as a temporary data storage buffer. This is the simplest register type.

6. Counters

A counter is a sequential circuit that goes through a predetermined sequence of states upon the application of clock pulses. The sequence of states can be binary, BCD, or any other sequence.

6.1 Asynchronous (Ripple) Counters

In an asynchronous counter, the flip-flops are not clocked by the same signal. The output of one flip-flop serves as the clock input for the next flip-flop in the chain.

• Design (3-bit Up Counter using T-FFs):

  • The first FF (LSB) is clocked by the external clock.
  • The output Q0 of the first FF clocks the second FF.
  • The output Q1 of the second FF clocks the third FF.
  • All T inputs are tied to HIGH (logic 1) to ensure they toggle on every clock edge.

• Operation: The change in state "ripples" through the chain of flip-flops.

• State Sequence (Up Count): 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000...

• Disadvantage: Propagation Delay. Because the clock signal propagates through each flip-flop, there is a cumulative delay. For high-frequency operation or a large number of bits, the outputs may not be stable or correct at the same time, leading to decoding errors.

6.2 Synchronous Counters

In a synchronous counter, all flip-flops are triggered by the same clock signal simultaneously. This eliminates the propagation delay problem of ripple counters.

• Design (3-bit Up Counter using JK-FFs):

  1. State Diagram/Table: Determine the sequence of states.
  2. Excitation Table: For each flip-flop, determine the required J and K inputs to transition from the present state to the next state.
  3. K-Maps: Derive simplified logic expressions for each J and K input in terms of the flip-flop outputs (Q2, Q1, Q0).
  4. Circuit Implementation: Connect the flip-flops and the derived combinational logic.

• Derived Logic for 3-bit Sync Up Counter:

  • J0 = K0 = 1
  • J1 = K1 = Q0
  • J2 = K2 = Q0·Q1

• Circuit:

• Advantage: All outputs change at the same time, making it much faster and more reliable than an asynchronous counter.

• Disadvantage: Requires more complex combinational logic as the number of bits increases.

6.3 Ring Counter

A ring counter is a special type of shift register where the output of the last flip-flop is connected back to the input of the first flip-flop.

• Structure: A SISO shift register with a feedback loop from the last output (Qn-1) to the first input (D0).

• Operation: A single '1' (or '0') is circulated around the register. It must be pre-loaded with a starting pattern (e.g., 1000).

• States: For an N-bit ring counter, there are N distinct states.

• Example (4-bit Ring Counter):

  • Sequence: 1000 → 0100 → 0010 → 0001 → 1000 ...

• Application: Used for timing and control sequence generation where only one output is active at a time.

6.4 Johnson Ring Counter (Twisted-Ring Counter)

A Johnson counter is a modified ring counter where the inverted output of the last flip-flop is connected back to the input of the first.

• Structure: Similar to a ring counter, but the feedback is from Q'n-1 to D0.

• Operation: The register fills with 1s from one side and then fills with 0s.

• States: For an N-bit Johnson counter, there are 2N distinct states.

• Example (4-bit Johnson Counter, starting from 0000):

  • Sequence: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000 ...

• Application: Can be used to generate multi-phase clock signals or as a divide-by-2N counter. It is self-starting (if it enters an unused state, it will eventually return to the main sequence) and requires simpler decoding logic than a binary counter.