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Unit 6 - Practice Quiz

ECE221

1 Which of the following best describes the primary function of a basic comparator circuit?

A. To amplify a small input signal linearly
B. To compare two input voltages and produce a digital-like output state
C. To filter out high-frequency noise from a signal
D. To generate a sine wave oscillation

2 In a standard Zero Crossing Detector (ZCD) using an op-amp, if the input is applied to the non-inverting terminal and the inverting terminal is grounded, what is the output when the input voltage is positive?

A.
B.
C.
D.

3 What is the main advantage of a Schmitt Trigger over a basic open-loop comparator?

A. Higher bandwidth
B. Lower power consumption
C. Immunity to noise due to hysteresis
D. Unity gain stability

4 In an inverting Schmitt Trigger, the Upper Threshold Point () and Lower Threshold Point () are determined by:

A. The input frequency
B. The feedback fraction and the saturation voltages
C. The slew rate of the op-amp
D. The input offset voltage

5 Calculate the hysteresis voltage () if and .

A.
B.
C.
D.

6 What is the function of a Zener diode when used in the feedback path of a comparator circuit?

A. To increase the slew rate
B. To act as a voltage limiter (clamp) for the output
C. To convert AC to DC
D. To provide linear amplification

7 A Voltage to Frequency Converter (VFC) effectively functions as a:

A. Voltage Controlled Oscillator (VCO)
B. Active Filter
C. Digital to Analog Converter
D. Current Mirror

8 Which application is best suited for a Frequency to Voltage (F-to-V) converter?

A. Generating clock pulses for a microcontroller
B. Digital Signal Processing
C. Tachometer (measuring motor speed)
D. Audio amplification

9 The resolution of an -bit Analog to Digital Converter (ADC) is given by:

A.
B.
C.
D.

10 Which type of Analog to Digital Converter (ADC) is the fastest?

A. Successive Approximation Register (SAR)
B. Dual Slope Integrating
C. Flash (Parallel) ADC
D. Counter Type ADC

11 What is the primary disadvantage of a Flash ADC?

A. Slow conversion speed
B. Complexity increases exponentially with bit depth (needs comparators)
C. Requires a clock signal
D. Cannot handle negative voltages

12 In a Weighted Resistor DAC, the resistor values are related by powers of:

A. 10
B. 2
C. e (natural log base)
D. The Fibonacci sequence

13 What is the main advantage of an R-2R Ladder DAC over a Weighted Resistor DAC?

A. It requires fewer resistors overall
B. It is faster
C. It uses only two specific resistor values, making fabrication easier and more precise
D. It provides higher output current

14 The process of converting a continuous analog signal into discrete time samples is called:

A. Quantization
B. Sampling
C. Encoding
D. Filtering

15 What is the purpose of the holding capacitor in a Sample and Hold (S/H) circuit?

A. To filter noise
B. To store the sampled voltage value while the ADC performs conversion
C. To generate the sampling clock
D. To couple the AC signal

16 In a Sample and Hold circuit, 'Aperture Time' refers to:

A. The time the switch stays closed
B. The time it takes for the capacitor to discharge
C. The delay between the hold command and the actual switch opening
D. The time required for the ADC to convert data

17 A Dual Slope ADC is preferred in digital multimeters because:

A. It is the fastest ADC available
B. It has excellent noise rejection, particularly for mains frequency (50/60Hz)
C. It requires no external clock
D. It uses the least amount of power

18 Which pin of the 555 timer is known as the 'Threshold' pin?

A. Pin 2
B. Pin 6
C. Pin 7
D. Pin 5

19 In a standard 555 timer block diagram, the internal resistive voltage divider consists of three resistors of what value?

A.
B.
C.
D.

20 What happens when the Trigger pin (Pin 2) of a 555 timer falls below ?

A. The output goes LOW
B. The output goes HIGH
C. The capacitor discharges
D. The chip resets

21 When a 555 timer is configured as a Monostable Multivibrator, the output pulse width () is given by:

A.
B.
C.
D.

22 Which of the following describes the 'Astable' mode of a 555 timer?

A. It produces a single pulse when triggered
B. It acts as a flip-flop holding one state
C. It generates a continuous square wave output (free-running)
D. It acts as a linear amplifier

23 In a 555 Astable Multivibrator with resistors , and capacitor , the charging time () is determined by:

A. and
B. and
C. and
D. and

24 Calculate the frequency of oscillation for a 555 astable circuit where , , and . (Use constant 1.44)

A.
B.
C.
D.

25 What is the function of the Reset pin (Pin 4) on a 555 timer?

A. It starts the timing cycle
B. It forces the output to LOW state regardless of other inputs when connected to ground
C. It adjusts the threshold voltage
D. It serves as the ground connection

26 Pin 5 (Control Voltage) of a 555 timer is often connected to ground through a capacitor. Why?

A. To filter out high-frequency noise that might alter the threshold levels
B. To increase the output current capability
C. To set the operating frequency
D. To protect the chip from over-voltage

27 According to the standard NE555 datasheet, what is the typical supply voltage range?

A. to
B. to
C. to
D. to

28 Based on the 555 datasheet, the 'Discharge' pin (Pin 7) is effectively:

A. An open-collector transistor to ground
B. A voltage source
C. A high-impedance input
D. A short circuit to

29 The Duty Cycle () of a standard 555 Astable circuit is given by . This implies that the duty cycle is always:

A. Exactly 50%
B. Less than 50%
C. Greater than 50%
D. Depending on the capacitor value

30 What are the three main functional blocks of a Phase Locked Loop (PLL)?

A. Amplifier, Rectifier, Filter
B. Phase Detector, Low Pass Filter, Voltage Controlled Oscillator (VCO)
C. Comparator, Integrator, Differentiator
D. Modulator, Transmitter, Receiver

31 In a PLL, what is the 'Lock Range'?

A. The range of frequencies where the PLL can initially acquire a lock
B. The range of frequencies over which the PLL can maintain lock once locked
C. The voltage range of the power supply
D. The maximum frequency of the VCO

32 In a PLL, what is the 'Capture Range'?

A. The range of frequencies where the PLL can acquire lock on an input signal from an unlocked state
B. The range of output voltages
C. The same as the lock range
D. The frequency of the free-running VCO

33 Which component in the PLL determines the dynamic characteristics (response speed and stability) of the loop?

A. The Phase Detector
B. The Low Pass Filter
C. The VCO
D. The Power Supply

34 If the input frequency is equal to the VCO free-running frequency in a PLL, the phase error voltage generated is:

A. Maximum
B. Zero
C. Infinite
D. Negative

35 Which of the following is a common application of a Phase Locked Loop (PLL)?

A. FM Demodulation
B. Voltage Amplification
C. Active Filtering
D. Digital Logic Gates

36 What is 'Quantization Error' in an ADC?

A. Error due to clock jitter
B. The difference between the actual analog input and the nearest available discrete digital value
C. Error caused by thermal noise
D. The delay in conversion

37 In a digital-to-analog converter, 'Monotonicity' means:

A. The output voltage always increases or stays the same as the digital input increases
B. The output is a mono audio signal
C. The device uses a single power supply
D. The linearity error is zero

38 What is the primary role of the 'Free-running frequency' () in a PLL?

A. It is the frequency of the VCO when no input signal is applied
B. It is the maximum frequency the PLL can reach
C. It is the frequency of the mains supply
D. It is the cut-off frequency of the filter

39 Which standard IC is a popular Phase Locked Loop?

A. IC 741
B. IC 555
C. NE/SE 565
D. LM 317

40 In a Successive Approximation (SAR) ADC, how many clock cycles are required for an -bit conversion?

A.
B.
C. $1$
D.

41 What is the phenomenon called when a signal is sampled at a frequency lower than twice its maximum frequency (), causing distortion?

A. Aliasing
B. Quantization
C. Hysteresis
D. Slewing

42 A Schmitt trigger is often used to convert:

A. Square waves to sine waves
B. Slowly varying or noisy waveforms into clean square waves
C. Digital signals to analog signals
D. Current to Voltage

43 If a 555 timer output can source or sink (per datasheet), what does this mean?

A. It consumes 200mA from the power supply continuously
B. It can directly drive loads like relays or small lamps up to 200mA
C. It requires 200mA input current to trigger
D. The frequency is 200 MHz

44 The voltage divider rule applied to the internal structure of the 555 timer establishes which two crucial reference voltages?

A. and
B. and
C. and
D. and

45 In a voltage limiter using a feedback resistor and parallel back-to-back Zener diodes, the output slope before limiting is determined by:

A. The Zener voltage
B. The open loop gain of the op-amp
C. The ratio of feedback resistor to input resistor (Closed loop gain)
D. The supply voltage

46 For a 4-bit DAC with a reference, what is the weight of the Least Significant Bit (LSB)?

A.
B.
C.
D.

47 The 'Droop Rate' in a sample and hold circuit is primarily caused by:

A. Leakage currents in the switch and capacitor
B. Low supply voltage
C. High frequency input
D. The gain of the buffer amplifier

48 Which Phase Detector type in a PLL is essentially an Exclusive-OR (XOR) gate?

A. Type I (Analog/Digital mixing)
B. Type II (Edge triggered)
C. Type III
D. Quadrature detector

49 Frequency synthesis using a PLL allows:

A. Generation of a stable frequency that is a multiple of a reference crystal frequency
B. Converting Voltage to Current
C. Filtering noise from audio
D. Storing digital data

50 What is the primary benefit of using a Schmitt Trigger on the input of a digital logic gate?

A. It increases the voltage level
B. It inverts the logic
C. It prevents false triggering caused by noisy input edges
D. It reduces power consumption