Unit 6: Field effect transistors and FET Biasing

1. Junction Field-Effect Transistor (JFET)

A JFET is a three-terminal semiconductor device that uses voltage to control the flow of current. It is a unipolar device, meaning its operation depends on the flow of only one type of charge carrier (either electrons or holes).

1.1 Construction

JFETs come in two types: n-channel and p-channel.

• n-Channel JFET:

  • A bar of n-type semiconductor material forms the channel between two terminals: the Source (S) and the Drain (D).
  • Two regions of p-type material are diffused on opposite sides of the n-type bar, forming the Gate (G). These two p-regions are internally connected.
  • The region between the two gate regions is the channel through which electrons flow from Source to Drain.
  TEXT

           Drain (D)
             |
        |----|----|
      G | p  | n  | p | G  <-- Gate terminals (connected internally)
        |----|----|
             |
          Source (S)
      (Schematic Cross-Section of n-Channel JFET)
      

• p-Channel JFET:

  • The construction is the inverse: a p-type channel with n-type gate regions.
  • Current is carried by holes.
  • All voltage and current polarities are reversed compared to the n-channel JFET.

1.2 Principle of Operation

1. V_GS = 0V, V_DS > 0V: When a voltage V_DS is applied between Drain and Source, a current I_D flows through the n-channel. The p-n junctions at the gate are reverse-biased, creating depletion regions that extend into the channel. As I_D flows, there is a voltage drop along the channel, making the reverse bias greater near the drain. The depletion region is therefore wider near the drain.
2. V_GS < 0V (for n-channel): Applying a negative voltage from Gate to Source (V_GS) increases the reverse bias on the p-n junction. This widens the depletion regions, further narrowing the conductive channel.
   • Controlling Current: A more negative V_GS makes the channel narrower, increasing its resistance and reducing the drain current I_D. Therefore, the gate voltage controls the drain current.
3. Pinch-off Voltage (V_P): As V_DS increases (for a fixed V_GS), the depletion regions widen. The value of V_DS at which the two depletion regions almost touch is called the pinch-off voltage, V_P. Beyond this point, an increase in V_DS does not cause a significant increase in I_D. The JFET is now in the saturation region.
4. Cutoff Voltage (V_GS(off)): The value of V_GS that makes the depletion regions touch and completely "pinch off" the channel, reducing I_D to almost zero, is the gate-source cutoff voltage, V_GS(off). For JFETs, V_P = -V_GS(off).

1.3 Characteristics

Drain Characteristics (Output Characteristics)

This is a plot of Drain Current (I_D) vs. Drain-Source Voltage (V_DS) for different values of V_GS.

• Ohmic Region (Linear Region): At low values of V_DS, the JFET behaves like a voltage-controlled resistor. I_D increases linearly with V_DS. The resistance is controlled by V_GS.
• Saturation Region (Active Region): When V_DS ≥ V_P, the channel is pinched off. I_D becomes nearly constant and is controlled by V_GS. This is the normal operating region for amplifiers. The maximum drain current, I_DSS, occurs when V_GS = 0V.
• Breakdown Region: If V_DS is increased too much, the gate-channel junction experiences avalanche breakdown, leading to a sharp increase in I_D which can damage the device.

Transfer Characteristics

This is a plot of Drain Current (I_D) vs. Gate-Source Voltage (V_GS) for a constant V_DS in the saturation region. This curve is defined by the Shockley Equation:

I_D = I_DSS * (1 - V_GS / V_GS(off))^2

• I_DSS: The maximum drain current when V_GS = 0V.
• V_GS(off): The gate-source cutoff voltage.
• The curve is non-linear (parabolic). It shows that as V_GS becomes more negative (for an n-channel device), I_D decreases, reaching zero at V_GS(off).

1.4 JFET Symbols

2. Metal-Oxide-Semiconductor FET (MOSFET)

MOSFETs are the most common type of FET. Their key feature is the insulated gate: a thin layer of Silicon Dioxide (SiO₂) separates the gate terminal from the channel, resulting in extremely high input impedance.

2.1 Depletion-Type MOSFET (D-MOSFET)

Construction

Similar to a JFET, a D-MOSFET has a pre-existing physical channel between the drain and source. The gate is a metal plate insulated from the channel by a SiO₂ layer.

      Gate (G)
      ||||||||||  <-- Metal
     -----------  <-- SiO2 Insulator
  S | n+ |  n   | n+ | D
     |    |      |    |
     |----|------|----|
     |       p-Substrate    |
     ----------------------
             Body (B)
(Schematic Cross-Section of n-Channel D-MOSFET)

Principle of Operation

The D-MOSFET can operate in two modes:

1. Depletion Mode (V_GS < 0V for n-channel):

   • A negative V_GS induces a positive charge in the n-channel.
   • This "pushes away" or depletes the free electrons in the channel, reducing its conductivity and decreasing I_D.
   • Operation is similar to an n-channel JFET.

2. Enhancement Mode (V_GS > 0V for n-channel):

   • A positive V_GS induces a negative charge in the n-channel.
   • This attracts more free electrons into the channel, enhancing its conductivity and increasing I_D beyond I_DSS.

Characteristics

• Drain Characteristics: Similar to JFET, but with additional curves for V_GS > 0V.
• Transfer Characteristics: The curve extends into the positive V_GS region. The Shockley equation still applies for the depletion region (V_GS ≤ 0).

D-MOSFET Symbols

2.2 Enhancement-Type MOSFET (E-MOSFET)

Construction

The E-MOSFET has no physical channel between the drain and source initially. The substrate extends all the way to the SiO₂ layer.

      Gate (G)
      ||||||||||  <-- Metal
     -----------  <-- SiO2 Insulator
  S | n+ |       | n+ | D
     |    |   p   |    |
     |----| Substrate-|----|
     |                  |
     ----------------------
             Body (B)
(Schematic Cross-Section of n-Channel E-MOSFET)

Principle of Operation

1. V_GS < V_T: With zero or a small positive V_GS, there is no conductive channel. Two back-to-back p-n junctions exist, so I_D is practically zero.
2. V_GS ≥ V_T (Threshold Voltage):
   • When V_GS reaches a positive value called the Threshold Voltage (V_T), it attracts minority carriers (electrons) from the p-substrate to the area just under the SiO₂ layer.
   • This forms a thin n-type inversion layer which acts as a channel. The channel is created or enhanced by the gate voltage.
   • Current I_D can now flow from drain to source.
   • A V_GS greater than V_T widens this induced channel, allowing more current to flow.

Characteristics

• Drain Characteristics: Similar to other FETs, but I_D is zero until V_GS exceeds V_T.

• Transfer Characteristics:

  • I_D is zero for V_GS < V_T.
  • For V_GS > V_T, the relationship is given by:
  TEXT

      I_D = k * (V_GS - V_T)^2
      

  • k is a device constant, dependent on its construction (k = μ_n * C_ox * (W/2L)).
  • V_T is the threshold voltage.

E-MOSFET Symbols

3. FET Biasing

Biasing establishes a stable DC operating point (Q-point), defined by I_DQ and V_DSQ, to ensure the FET operates correctly in the desired region (usually saturation/active) for amplification.

3.1 Fixed-Bias Configuration

Circuit

A simple biasing circuit where the gate is connected to a fixed DC voltage V_GG through a resistor R_G. For DC analysis, no current flows into the gate (I_G ≈ 0), so the voltage drop across R_G is zero. Therefore, V_GS = V_GG.

          +V_DD
            |
            R_D
            |
      |-----| D
      |     G -----|
  V_GG--R_G--|      S |
      |     |--------|
      |              |
     GND            GND

DC Analysis

1. Input Loop (Gate-Source):

   • Since I_G ≈ 0, V_R_G = I_G * R_G ≈ 0.
   • Applying KVL: -V_GG - V_GS = 0 => V_GS = -V_GG (for the polarity shown).
   • The Q-point value of V_GS is fixed by V_GG.

2. Output Loop (Drain-Source):

   • Applying KVL: +V_DD - I_D * R_D - V_DS = 0 => V_DS = V_DD - I_D * R_D.
   • I_D is determined by the fixed V_GS value using the device's transfer characteristic (e.g., Shockley equation).

Stability

• Poor Stability: FET parameters like I_DSS and V_GS(off) vary significantly between devices of the same part number and with temperature.
• Since V_GS is fixed, any variation in the transfer curve will cause a large shift in the Q-point (I_DQ), making this configuration highly unstable and rarely used in practice.

3.2 Self-Bias Configuration

Circuit

This configuration provides improved stability by using a source resistor R_S to generate the biasing voltage V_GS. The gate is connected to ground via R_G.

          +V_DD
            |
            R_D
            |
      |-----| D
      |     G -----|
      |--R_G--|      S |
      |     |--------|
     GND             |
                     R_S
                     |
                    GND

DC Analysis

1. Input Loop (Gate-Source):

   • I_G ≈ 0, so the voltage at the gate V_G = 0V.
   • The voltage at the source is V_S = I_D * R_S.
   • V_GS = V_G - V_S = 0 - I_D * R_S => V_GS = -I_D * R_S.
   • This equation shows that V_GS is now dependent on the drain current I_D. This provides negative feedback, stabilizing the Q-point. If I_D tries to increase, V_S increases, making V_GS more negative, which in turn reduces I_D.

2. Output Loop (Drain-Source):

   • V_DD - I_D * R_D - V_DS - I_D * R_S = 0 => V_DS = V_DD - I_D * (R_D + R_S).

Finding the Q-point

• Graphical Method:

  1. Plot the JFET's transfer characteristic curve (I_D vs. V_GS).
  2. Plot the self-bias line given by the equation I_D = -V_GS / R_S. This is a straight line passing through the origin with a slope of -1/R_S.
  3. The intersection of the transfer curve and the self-bias line is the Q-point (I_DQ, V_GSQ).

• Mathematical Method:

  1. Substitute V_GS = -I_D * R_S into the Shockley equation:
     I_D = I_DSS * (1 - (-I_D * R_S) / V_GS(off))^2
  2. Solve this quadratic equation for I_D to find I_DQ.

3.3 Voltage-Divider Biasing

Circuit

This is the most stable biasing configuration. A voltage divider (R1 and R2) sets a fixed voltage V_G at the gate.

          +V_DD
            |
            R_D
            |
      |--R1--| D
      |     | -----|
      |-----G------|      S |
      |     |--------|
      |--R2--|        |
      |              R_S
     GND             |
                    GND

DC Analysis

1. Input Loop (Gate-Source):

   • The gate voltage V_G is determined by the voltage divider:
     V_G = (R2 / (R1 + R2)) * V_DD
   • Applying KVL around the gate-source loop:
     V_G - V_GS - I_D * R_S = 0 => V_GS = V_G - I_D * R_S.

2. Output Loop (Drain-Source):

   • Same as self-bias: V_DS = V_DD - I_D * (R_D + R_S).

Finding the Q-point

• Graphical Method:

  1. Plot the JFET's transfer characteristic curve.
  2. Plot the load line from the equation I_D = (V_G - V_GS) / R_S.
     • To plot the line, find two points:
       • If V_GS = 0, then I_D = V_G / R_S.
       • If I_D = 0, then V_GS = V_G.
  3. The intersection of the transfer curve and the load line is the Q-point (I_DQ, V_GSQ).

• Stability: This circuit is stable because V_G is typically much larger than V_GS. Therefore, I_D ≈ (V_G / R_S), making the drain current less dependent on the JFET's characteristics and more dependent on the fixed resistor values.

4. Understanding FET Datasheets

A datasheet provides all the necessary information about a component, including its features, maximum ratings, electrical characteristics, and typical performance curves.

Key Sections of a Datasheet

1. General Description & Features: A brief overview of the device type, its intended applications (e.g., "N-Channel JFET for general purpose audio and switching"), and key features.

2. Absolute Maximum Ratings: These are stress ratings. Exceeding them, even for a moment, can cause permanent damage.

   • V_DS, V_DG: Maximum Drain-Source and Drain-Gate voltages.
   • V_GS: Maximum Gate-Source voltage.
   • I_D: Maximum continuous Drain current.
   • P_D: Maximum Power Dissipation at a specified temperature. This value must be derated for higher temperatures.

3. Electrical Characteristics: These define the device's performance under specific test conditions (e.g., T_A = 25°C). They are usually given as minimum, typical, and maximum values. The wide range between min and max values is critical for robust circuit design.

   • OFF Characteristics:

     • V_(BR)GSS: Gate-Source Breakdown Voltage. The V_GS at which the gate junction breaks down.
     • I_GSS: Gate Reverse Current. The leakage current into the gate when it is reverse-biased. It's very low due to high input impedance.
     • V_GS(off): Gate-Source Cutoff Voltage. The V_GS required to reduce I_D to a very small value. This has a wide range.

   • ON Characteristics:

     • I_DSS: Zero-Gate-Voltage Drain Current. The drain current when V_GS = 0V and V_DS is a specified value. This also has a very wide range.

   • Small-Signal Characteristics (for AC analysis):

     • g_fs or y_fs: Forward Transfer Admittance (Transconductance). The ratio of change in I_D to the change in V_GS. g_fs = ΔI_D / ΔV_GS. It indicates the gain of the FET.
     • g_os or y_os: Output Admittance. The ratio of change in I_D to the change in V_DS. Its reciprocal is the drain resistance r_d.
     • C_iss, C_rss, C_oss: Input, Reverse Transfer, and Output Capacitances. These are important for high-frequency applications.

4. Characteristic Curves: Graphs showing typical device behavior.

   • Output Characteristics (I_D vs V_DS).
   • Transfer Characteristics (I_D vs V_GS).
   • Transconductance vs. V_GS.
   • Capacitance vs. Voltage.

5. Datasheet Analysis: 2N5457, 2N5458, 2N5459 JFETs

These are popular general-purpose N-Channel JFETs. They are essentially the same device but are binned (sorted) based on their V_GS(off) and I_DSS values. Let's analyze a typical datasheet (e.g., from onsemi).

Absolute Maximum Ratings (T_A = 25°C)

• Interpretation: Do not apply more than 25V between any two terminals. The negative sign for V_GS indicates the reverse bias limit.

OFF Characteristics

• Interpretation: The most critical parameter for biasing is V_GS(off). For a 2N5457, one device might turn off at -0.5V, while another from the same batch might require -6.0V. This huge variation makes fixed-biasing impossible for production circuits.

ON Characteristics

• Interpretation: Similar to V_GS(off), the range for I_DSS is very wide. A 2N5457 can have a max current anywhere from 1.0 mA to 5.0 mA. Any biasing circuit must be designed to work reliably across this entire range. This is why self-bias and voltage-divider bias, which provide stability against parameter variations, are essential.

Small-Signal Characteristics

• Interpretation: g_fs (or transconductance) is the gain parameter. Its value also varies significantly. Knowing this range is crucial for designing amplifiers with predictable gain.

6. Recent Trends in Electronics

The field of electronics is constantly evolving, driven by the need for smaller, faster, and more power-efficient devices.

1. FinFETs and Gate-All-Around (GAA) FETs

As traditional planar MOSFETs were scaled down to nanometer sizes, they began suffering from "short-channel effects" like current leakage and poor gate control.

• FinFET (Fin Field-Effect Transistor):

  • Structure: The channel is a raised 3D "fin" of silicon. The gate is wrapped around this fin on three sides.
  • Advantage: This multi-gate structure provides much better electrostatic control over the channel, significantly reducing leakage current and allowing for faster switching speeds at lower power. FinFETs are the dominant technology in modern CPUs, GPUs, and smartphone chips (e.g., 14nm, 10nm, 7nm nodes).

• GAAFET (Gate-All-Around FET):

  • Structure: The next evolution after FinFETs. The gate material completely surrounds the channel, which is often in the form of multiple horizontal nanowires or nanosheets.
  • Advantage: Provides the ultimate level of gate control (from all four sides), enabling further scaling to 3nm and beyond. GAAFETs promise even better performance and lower power consumption.

2. Wide Bandgap (WBG) Semiconductors

For decades, silicon (Si) has been the workhorse of the semiconductor industry. However, for high-power and high-frequency applications, its physical limits are being reached. Wide bandgap materials are the solution.

• Materials: Silicon Carbide (SiC) and Gallium Nitride (GaN).
• Properties (vs. Silicon):
  • Higher Breakdown Voltage: Can handle much higher voltages in a smaller device size.
  • Higher Thermal Conductivity: Can operate at much higher temperatures.
  • Higher Switching Speed: Can turn on and off much faster, leading to more efficient power conversion.
• Applications:
  • SiC: Dominating in high-power applications like electric vehicle (EV) inverters, charging stations, and industrial motor drives.
  • GaN: Excelling in high-frequency power electronics (compact and efficient laptop/phone chargers) and RF applications like 5G base stations and radar systems.

3. Flexible and Wearable Electronics

This trend moves away from rigid silicon wafers to create electronics on flexible or stretchable substrates.

• Key Technologies:
  • Organic FETs (OFETs): Using organic molecules or polymers as the semiconductor material.
  • Thin-Film Transistors (TFTs): Built on flexible substrates like plastic.
  • Advanced Materials: Graphene, carbon nanotubes.
• Applications:
  • Flexible OLED displays for foldable phones and rollable TVs.
  • Wearable health sensors that conform to the skin (e.g., E-skin, smart patches).
  • Smart textiles with integrated electronics.
  • Low-cost, disposable electronics for IoT sensors and smart packaging.