Unit 6 - Practice Quiz

The three terminals of a JFET are the Drain (D), Source (S), and Gate (G). These terminals control the flow of current through the device's channel.

Applying a negative voltage to the gate of an n-channel JFET reverse-biases the gate-source p-n junction. This increases the depletion region, which narrows the conductive channel and reduces current flow.

The gate-to-source cutoff voltage, , is the specific negative value of (for an n-channel JFET) that completely 'pinches off' the channel and stops the flow of drain current.

Unlike an E-MOSFET, a D-MOSFET is fabricated with a physical conductive channel already existing between the drain and source. This allows current to flow even with zero gate voltage.

D-MOSFETs are considered 'normally on' because their pre-existing physical channel allows drain current to flow as soon as a drain-source voltage is applied, even with the gate-source voltage at zero.

The solid line in the D-MOSFET symbol signifies the presence of a continuous, pre-existing physical channel between the drain and source terminals.

The key difference is that an E-MOSFET is built without a physical channel. A channel must be induced (enhanced) by applying a sufficient gate voltage before current can flow from drain to source.

An E-MOSFET is a 'normally off' device. A conductive channel is only formed when the gate-to-source voltage exceeds a minimum value called the threshold voltage (), allowing current to flow.

The dashed or broken line in the E-MOSFET symbol signifies that there is no pre-existing physical channel; one must be induced by the gate voltage for the device to conduct.

The 'fixed-bias' name comes from the fact that it uses a dedicated DC voltage source, , to set a fixed value for , which is independent of the drain circuit.

While simple to design, the fixed-bias circuit's operating point (Q-point) is very sensitive to variations in the FET's parameters (like and ), making it unstable.

In self-bias, the drain current () flows through , creating a positive voltage at the source (). Since the gate is at 0V, , resulting in a negative that biases the FET.

connects the gate to ground. Since negligible DC current flows into the gate, there is no voltage drop across , holding the gate at 0V. Its large value ensures a high input impedance for the amplifier.

The resistors and form a voltage divider that sets a fixed, positive DC voltage at the gate terminal (). This makes the overall biasing less dependent on the FET's characteristics.

Voltage-divider biasing provides the most stable operating point because the gate voltage is set firmly by the divider, making the circuit's Q-point largely independent of the FET's transfer characteristics.

stands for Drain-to-Source Saturation Current. It is a key parameter that represents the maximum drain current a JFET will pass, which occurs when is zero.

The 'Absolute Maximum Ratings' section specifies the stress limits (e.g., maximum , , power dissipation) beyond which the device may be permanently damaged. These are not recommended operating values.

The 2N5457/58/59 series are well-known general-purpose N-Channel Junction Field-Effect Transistors, primarily used for amplification and switching applications.

FinFETs are multi-gate, non-planar transistors where the gate wraps around the channel (the 'fin'). This structure provides better control, reducing leakage current and enabling the creation of smaller, faster, and more energy-efficient integrated circuits.

Gallium Nitride (GaN) is a modern semiconductor material that can operate at much higher voltages, temperatures, and frequencies than traditional silicon. This makes it ideal for new trends in power supplies, electric vehicles, and 5G communications.

The drain current in the saturation region is given by Shockley's equation: . Plugging in the values: mA.

For a JFET, saturation begins when . The pinch-off condition occurs at . For a p-channel JFET, is negative. So, V. The device enters saturation when becomes more negative than -3 V.

A D-MOSFET can operate in enhancement mode with . The current is calculated using the same transconductance equation: mA.

The drain current for an E-MOSFET in saturation is . We need to solve for : . This simplifies to . Taking the square root, (since must be ). Therefore, V.

The key difference is that a D-MOSFET is built with a physical n-type channel already diffused between the drain and source. This allows current to flow even with . A negative depletes this channel, while a positive enhances it. An E-MOSFET has no initial channel and requires a positive to create one.

The correct option follows directly from the given concept and definitions.

In a self-bias configuration, the gate is at 0V (since ) and the source is at . The gate-source voltage is . Rearranging this equation to express as a function of gives the bias line equation: . With kΩ, this becomes .

The correct option follows directly from the given concept and definitions.

The temperature increase above the reference is . The reduction in power dissipation is the derating factor multiplied by this temperature change: mW. The maximum power at 75°C is the initial max power minus the reduction: mW.

The Q-point is the intersection of the transfer curve and the bias line . Increasing makes the slope of the bias line () less steep (closer to the horizontal axis). This causes the intersection point on the transfer curve to shift to a lower value of and a more negative value of .

When the microcontroller outputs 5 V, V. Since this is greater than V, the MOSFET turns on. When used as a switch, the goal is to have a very low voltage drop across it (). Since a large is applied and will be very small, the condition for ohmic operation () is met. This low ensures minimal power loss in the switch.

The goal is to select a device where the desired operating current (5 mA) is roughly in the middle of its specified range. For the 2N5457, 5 mA is at the maximum limit. For the 2N5459, 5 mA is near the minimum limit. For the 2N5458, whose range is 2-9 mA, 5 mA is almost exactly in the center, making it the most suitable choice for predictable biasing and performance.

The main advantage of voltage-divider bias is stability. The gate voltage is held relatively constant by the divider resistors. This makes the operating point (, ) much less dependent on the FET's parameters (, ), which can vary significantly between devices. This is crucial for mass production and predictable circuit performance.

In a self-bias circuit, the relationship between the Q-point parameters is given by the bias line equation . We can rearrange this to solve for : . Substituting the given values: Ω or 2 kΩ.

In fixed-bias, is set to a constant value. Since the JFET transfer characteristic ( vs ) varies significantly from one device to another (due to manufacturing spread in and ), a fixed will result in a widely varying drain current . This makes the Q-point unstable and unpredictable.

Transconductance is defined by the relationship . As gets closer to , the term approaches zero. Consequently, decreases and becomes zero at pinch-off. The maximum transconductance, , occurs at .

Forward Transfer Admittance, denoted as , is the common-source AC forward transfer admittance. In the low-frequency region where capacitive effects are negligible, this parameter is equivalent to the AC transconductance, . It represents the ratio of the change in drain current to the change in gate-source voltage (). Its unit, Siemens (S) or mhos, is the unit of conductance.

This demonstrates the stability of voltage-divider bias. The gate voltage is fixed by the resistors. The source voltage is . The relation is . If a higher FET causes to increase, increases, making more negative. This more negative counteracts the initial increase in , providing negative feedback and keeping relatively stable.

stands for Breakdown Voltage from Gate to Source, with the drain shorted to the source. It specifies the maximum reverse-bias voltage that can be applied to the gate-source p-n junction before avalanche breakdown occurs, which would permanently damage the device. The negative sign indicates the polarity for reverse bias on an n-channel JFET.

In a FinFET, the traditional flat (planar) channel is replaced by a three-dimensional silicon fin that rises vertically from the substrate. The gate electrode is wrapped around this fin on three sides (left, top, and right). This multi-gate structure gives the gate much stronger control over the channel, which significantly reduces short-channel effects and leakage currents, allowing for smaller and more efficient transistors.

Two main effects occur with increasing temperature in a JFET. First, the carrier mobility () decreases due to increased lattice scattering, which reduces conductivity and thus . Second, the magnitude of the pinch-off voltage () decreases. Both effects contribute to reducing the drain current for a given . The decrease in mobility is typically the more dominant effect.

Similar to the Early effect in BJTs, channel length modulation in FETs accounts for the finite output resistance in the saturation region. It is modeled by multiplying the ideal current equation by a factor , where is the channel length modulation parameter and is the inverse of the Early Voltage, . This factor models the slight increase in with due to the effective shortening of the channel length.

The D-MOSFET can operate in both depletion mode () and enhancement mode (). The same transconductance equation applies: . Here, is equivalent to . Plugging in the values:
mA.

The key feature of any MOSFET is the insulated gate, typically made of silicon dioxide (). This insulating layer prevents significant DC current from flowing into the gate, regardless of whether is positive or negative (within its operating limits). Therefore, the input impedance is extremely high (typically to ) in both depletion and enhancement modes.

This phenomenon is known as the body effect. The threshold voltage depends on the source-to-body voltage, . When is positive (source potential is higher than body), the depletion region under the channel widens, requiring a larger gate voltage to form the inversion layer. This increases the effective threshold voltage. The new threshold voltage is given by , where is the threshold voltage for . Since , will increase.

A P-channel E-MOSFET turns on when its gate-source voltage () is more negative than its threshold voltage (, which is negative). By connecting the source to and the gate to ground, . As long as is more negative than , the device will be ON by default. Applying a high control voltage (close to ) to the gate makes , turning the device OFF.

In a fixed-bias configuration, the gate-source voltage is determined solely by the biasing voltage source, so V. For the new JFET, we use its parameters with the fixed :
mA. This significant change highlights the poor Q-point stability of the fixed-bias configuration.

In this configuration, V. The condition for saturation is , which means must be V. The drain voltage is . Let's calculate the saturation current: mA. If this current were to flow, would be V, which is impossible. The circuit cannot supply this much current and maintain the saturation condition. Therefore, the MOSFET is driven hard into the ohmic region, where is very small and the current is limited by the external resistor .

The self-bias circuit provides stability via negative feedback. The bias line is . A large makes this line more horizontal on the transfer characteristics graph. The intersection of this nearly horizontal line with different JFET transfer curves (due to parameter spread) will occur at roughly the same value. The circuit essentially forces the drain current to be stable, while the adjusts to accommodate the specific JFET.

The correct option follows directly from the given concept and definitions.

The resistor , essential for DC biasing, introduces negative feedback for AC signals (degeneration), which reduces the amplifier's voltage gain. A bypass capacitor is chosen to have a very low impedance at signal frequencies. It effectively shorts the source terminal to ground for AC signals, while not affecting the DC bias condition. This removes the degenerative feedback, maximizing the AC voltage gain.

An N-channel JFET operates with . In contrast, an N-channel E-MOSFET requires to turn on. In a voltage-divider circuit, . Therefore, the condition to turn on the E-MOSFET is , which can be rearranged to . The gate voltage must be sufficiently positive to overcome both the source voltage () and the device's inherent threshold voltage.

The drain current is given by . The parameter variation is captured in , which can range from 0 to . If the fixed gate voltage is designed to be much larger than the maximum magnitude of (i.e., ), the term becomes negligible in comparison. This makes , which means the drain current is determined almost entirely by the external, stable resistor values and supply voltage, making it independent of the JFET's characteristics.

The correct option follows directly from the given concept and definitions.

The Total Gate Charge () represents the total charge required to switch the device state. The fundamental relationship between charge (), current (), and time () is . The gate driver provides the current. Therefore, the minimum switching time can be estimated as .
ns. The parameter is a more practical measure for switching time calculation than simple capacitance because it accounts for the Miller effect.

The correct option follows directly from the given concept and definitions.

The wide specified range for key parameters like and means that two different 2N5457 transistors can have vastly different transfer characteristics. This device-to-device variation will cause the operating point (Q-point) to shift significantly in simple biasing circuits. A robust design must use a biasing scheme like voltage-divider or source-follower bias to stabilize the drain current against these variations, ensuring predictable circuit performance.

Maximum transconductance, , occurs at and is given by the formula . Using the provided typical values:

• 2N5457: mS
• 2N5458: mS
• 2N5459: mS
  The calculation shows a clear trend: the 2N5459, with the highest current and pinch-off voltage, also possesses the highest transconductance, making it suitable for applications requiring higher gain.

The defining innovation of the FinFET is its three-dimensional structure. The channel is no longer a flat layer but a vertical fin of silicon. The gate electrode is wrapped around this fin on three sides (top and both sides). This multi-gate structure gives the gate much stronger control over the entire channel, significantly reducing short-channel effects like leakage current (off-state current) and allowing for better performance at smaller scales. While other options like high-k dielectrics are also used, the 3D fin is the key structural change.

The Gate-All-Around (GAA) architecture is the next step in transistor evolution. In a GAAFET, the gate material fully encloses the channel (which may be a nanowire or a stack of nanosheets). This provides gate control from all four sides, as opposed to the three sides in a FinFET. This complete control is electrostatically ideal, allowing for maximum suppression of short-channel effects and enabling further scaling of transistors to smaller dimensions with better performance and lower power leakage.