Unit 6: Assembly Techniques and Packaging of VLSI chips

1. Introduction to Packaging and the Packaging Process

1.1 What is IC Packaging?

An integrated circuit (IC) or "die" is a fragile, microscopic circuit fabricated on a silicon wafer. It is too small and delicate to be handled directly or connected to a printed circuit board (PCB). IC Packaging is the final stage of semiconductor manufacturing, where the die is encapsulated in a supportive case that protects it from the environment and allows it to be electrically connected to external circuits. This "package" is what we typically recognize as a "chip."

The process of packaging is also known as assembly, as it involves assembling the die, a leadframe or substrate, and an encapsulant into a finished product.

1.2 Key Functions of an IC Package

The package is not merely a container; it performs several critical functions:

1. Electrical Connection:

   • Signal and Power Distribution: Provides conductive paths (pins, leads, solder balls) to transmit signals and power between the IC die and the PCB.
   • Signal Integrity: The package must be designed to minimize electrical parasitics (resistance, capacitance, inductance) that can degrade signal quality, cause delays, and introduce noise.

2. Mechanical Protection:

   • Structural Support: Protects the fragile silicon die from mechanical shock, vibration, and physical damage during handling and operation.
   • Coefficient of Thermal Expansion (CTE) Matching: Acts as an intermediary to manage the stress caused by the mismatch in thermal expansion between the silicon die and the PCB material.

3. Thermal Management:

   • Heat Dissipation: The IC generates significant heat during operation. The package must provide an efficient path for this heat to be conducted away from the die to the surrounding environment, often with the help of a heat sink. This prevents the chip from overheating and failing.

4. Environmental Protection:

   • Hermetic Sealing: Protects the die from moisture, dust, corrosive chemicals, and other environmental contaminants that could cause short circuits or material degradation.

1.3 The IC Assembly and Packaging Process Flow

The journey from a completed silicon wafer to a packaged chip involves several sequential steps:

1. Wafer Mounting: The finished wafer is mounted on a sticky adhesive film (dicing tape) that is stretched over a frame. This holds the individual dice in place during sawing.

2. Wafer Dicing (or Singulation): The wafer is cut into individual dice. This is typically done using a high-precision diamond-tipped saw that cuts along the non-functional "scribe lines" between the dice.

3. Die Attach (or Die Bonding): The singulated dice that have passed wafer-level testing ("known good die") are picked from the dicing tape and attached to the package substrate or leadframe. This is commonly done using:

   • Epoxy adhesive: A polymer-based glue.
   • Solder: For high thermal conductivity applications.

4. Wire Bonding / Interconnection: Electrical connections are made between the I/O pads on the die and the corresponding pads on the package substrate/leadframe. The most common methods are:

   • Wire Bonding: Ultra-fine gold (Au) or copper (Cu) wires are attached one by one using a combination of heat, pressure, and ultrasonic energy.
   • Flip-Chip: The die is flipped upside down, and its I/O pads, which have solder bumps, are directly connected to the package substrate. This offers shorter electrical paths and better performance.

5. Encapsulation (or Molding): The die and wire bonds are encapsulated in a protective material, typically an epoxy molding compound. This provides mechanical and environmental protection. The process, called transfer molding, involves injecting molten plastic into a mold cavity containing the die and leadframe.

6. Deflashing/Trimming: Excess molding compound (flash) is removed from the package. For leadframe-based packages, the leads are separated from the frame (trimming) and formed into their final shape (e.g., J-bend, Gull-wing).

7. Solder Ball Attach (for BGA packages): For Ball Grid Array (BGA) packages, tiny solder balls are precisely attached to the pads on the bottom of the package substrate. These balls will be used to mount the package to the PCB.

8. Marking: The package is marked with the manufacturer's name, part number, date code, and other identifying information, usually with a laser.

9. Final Test: The packaged chip undergoes a final round of extensive electrical testing to ensure it meets all performance specifications and has not been damaged during the assembly process.

2. Package Design Considerations

Designing a package is a complex multidisciplinary challenge involving a trade-off between performance, reliability, and cost.

2.1 Electrical Considerations

• Signal Integrity: The package interconnects act as transmission lines. Poor design can lead to signal reflection, crosstalk (interference between adjacent lines), and attenuation, corrupting the data.
• Power Integrity: The power distribution network (PDN) within the package must provide stable, low-noise voltage to the die. Package inductance can cause voltage drops (L * di/dt) during high-speed switching, leading to performance issues. Decoupling capacitors are often integrated into the package substrate to mitigate this.
• Parasitics: Every physical connection has parasitic resistance (R), capacitance (C), and inductance (L).
  • Inductance (L): Long wires or leads have higher inductance, which is detrimental to high-speed signals and power delivery. Flip-chip and BGA packages offer lower inductance.
  • Capacitance (C): Capacitance between signal lines causes crosstalk. Capacitance to ground planes can slow down signal switching speeds.

2.2 Mechanical and Material Considerations

• Coefficient of Thermal Expansion (CTE): Different materials expand and contract at different rates with temperature changes. Silicon has a low CTE (~3 ppm/°C), while PCB materials (like FR-4) have a much higher CTE (~17 ppm/°C). The package must absorb the resulting stress to prevent solder joint fatigue, die cracking, or delamination.
• Form Factor: The physical size (length, width, height) of the package must fit the application's constraints (e.g., mobile devices require very thin, small-footprint packages).
• Moisture Sensitivity Level (MSL): Plastic packages can absorb moisture from the air. During soldering (reflow), this trapped moisture can turn into steam and expand rapidly, causing internal damage ("popcorning"). Packages are rated by their MSL, which dictates handling and storage requirements.

2.3 Thermal Considerations

• Heat Dissipation: All electrical power consumed by the chip is eventually converted into heat. This heat must be efficiently removed to keep the junction temperature (T_j) of the transistors below their maximum operating limit.
• Thermal Resistance (θ): This is a measure of how difficult it is for heat to flow from one point to another. The key metrics are:
  • θ_jc (Theta-junction-to-case): Thermal resistance from the die to the package surface. A lower value is better.
  • θ_ja (Theta-junction-to-ambient): Thermal resistance from the die to the surrounding air. This is the overall metric for thermal performance.
• Cooling Solutions: For high-power chips, the package design may incorporate features like integrated heat spreaders (IHS) or exposed die pads to facilitate the attachment of external heat sinks.

2.4 Cost Considerations

Cost is a primary driver. It is influenced by:

• Materials: Gold wires are more expensive than copper. Advanced organic substrates are more costly than simple leadframes.
• Process Complexity: Flip-chip and 3D packaging are more complex and have lower throughput than traditional wire bonding, increasing cost.
• Yield: The percentage of good, functioning packages produced. A low-yield process is prohibitively expensive.

3. Various Package Types

Packages can be classified based on their mounting technology, I/O placement, and complexity.

3.1 Classification by Mounting Technology

• Through-Hole Technology (THT): The package has long leads that are inserted through holes drilled in the PCB and then soldered on the other side.
  • Pros: Strong mechanical bond.
  • Cons: Low I/O density, requires drilling holes in the PCB, not suitable for automated high-volume assembly. Mostly legacy technology.
• Surface Mount Technology (SMT): The package is mounted directly onto the surface of the PCB. The leads or solder balls are soldered to pads on the board.
  • Pros: Higher I/O density, smaller size, allows for components on both sides of the PCB, ideal for automation.
  • Cons: Mechanical bond is less robust than THT.

3.2 Lead-based Packages (Perimeter I/O)

These packages have their input/output (I/O) connections arranged around the perimeter.

• Dual In-line Package (DIP): A THT package with two parallel rows of pins. The original IC package, now used mostly for prototyping and legacy systems.
• Small Outline Package (SOP / SOIC): An SMT version of the DIP with "gull-wing" shaped leads that bend out from the package body.
• Quad Flat Package (QFP): An SMT package with leads on all four sides, allowing for a higher pin count than SOIC. Lead pitch (spacing) can be very fine.

3.3 Array-based Packages (Area I/O)

These packages use the entire bottom surface area for I/O connections, enabling much higher density.

• Pin Grid Array (PGA): A THT package with a grid of pins on its underside. Historically used for high-pin-count microprocessors.
• Ball Grid Array (BGA): An SMT package that replaces pins with an array of solder balls for interconnection.
  • Advantages: Very high I/O density, excellent electrical performance due to short connections (low inductance), self-centering during solder reflow.
• Land Grid Array (LGA): Similar to a BGA but uses flat conductive pads ("lands") instead of solder balls. Connection is made via a socket with spring-loaded pins or by soldering directly to the PCB. Used in modern CPUs (e.g., Intel).

3.4 Advanced Packaging Technologies

• Flip-Chip: Instead of wire bonds, solder bumps are placed on the die's I/O pads. The die is "flipped" over and directly attached to the package substrate. This provides the shortest possible electrical path, resulting in superior performance for high-frequency applications.
• Wafer-Level Packaging (WLP): The entire packaging process (interconnection, encapsulation) is performed at the wafer level before dicing. This results in a package that is nearly the same size as the die itself (Chip Scale Package or CSP). It is highly cost-effective for low-I/O devices like those in mobile phones.
• System-in-Package (SiP): Multiple ICs (e.g., a processor and memory), and often passive components, are integrated into a single package. They are connected via a substrate, not on the same piece of silicon. This allows for the integration of components made with different process technologies.
• 2.5D and 3D ICs:
  • 2.5D: Multiple dice are placed side-by-side on a common silicon base called an "interposer," which provides high-density wiring between them.
  • 3D IC: Dice are stacked vertically and interconnected using Through-Silicon Vias (TSVs), which are vertical conductive channels running through the silicon die. This offers the ultimate in integration density and performance by dramatically shortening interconnects.

4. Prototype Fabrication of Monolithic Components (Front-End Process Review)

4.1 What is a Monolithic IC?

A monolithic IC (from the Greek monos, meaning "single," and lithos, meaning "stone") is an electronic circuit where all active components (transistors, diodes) and passive components (resistors, capacitors) are fabricated and interconnected on a single, continuous piece of semiconductor material, typically silicon. This is in contrast to a hybrid circuit, where individual components are attached to a common substrate.

4.2 Core Fabrication Steps

The creation of monolithic devices is a complex sequence of patterning, adding, and removing materials. The core steps are:

1. Substrate Preparation: Starting with a high-purity, single-crystal silicon wafer.
2. Oxidation: Growing a thin, uniform layer of high-quality Silicon Dioxide (SiO₂) on the wafer surface. SiO₂ acts as an excellent insulator and a mask for subsequent steps.
3. Photolithography: The process of transferring a geometric pattern from a photomask to the wafer surface.
   • Apply photoresist (a light-sensitive polymer).
   • Expose to UV light through the mask, changing the solubility of the resist.
   • Develop the resist to remove either the exposed (positive resist) or unexposed (negative resist) areas, creating a patterned mask.
4. Etching: Selectively removing material (e.g., SiO₂) from areas not protected by the photoresist mask. Can be "wet" (using chemicals) or "dry" (using plasma).
5. Doping: Introducing impurity atoms (dopants) into the silicon to change its electrical properties (create n-type or p-type regions).
   • Diffusion: Dopants are introduced at high temperatures and spread out in the silicon.
   • Ion Implantation: Dopant ions are accelerated and fired into the silicon. This method is more precise and controllable.
6. Deposition: Adding thin films of material onto the wafer.
   • Chemical Vapor Deposition (CVD): A chemical reaction of gases produces a solid film on the wafer. Used for dielectrics and polysilicon.
   • Physical Vapor Deposition (PVD) / Sputtering: Used to deposit metal layers for interconnects.
7. Metallization: Depositing and patterning metal (typically aluminum or copper) to form the wires that connect the components on the chip.

5. Prototype Fabrication of Specific Devices

The following are simplified process flows for creating fundamental monolithic components.

5.1 Diode Fabrication (p-n Junction)

A simple p-n junction diode can be fabricated by creating an n-type region within a p-type substrate.

Process Flow:

1. Start: p-type silicon wafer.
2. Oxidation: Grow a layer of SiO₂ on the surface.
3. Lithography (Mask 1): Pattern the SiO₂ to open a window where the n-type region will be formed.
4. Doping: Introduce n-type dopants (e.g., Phosphorus) through the window via diffusion or ion implantation. This creates the n-region, forming a p-n junction just below the surface.
5. Oxidation: Re-grow oxide to passivate the surface.
6. Lithography (Mask 2): Open contact windows through the oxide to both the n-region (cathode) and the p-substrate (anode).
7. Metallization: Deposit a layer of metal (e.g., Aluminum) over the entire surface.
8. Lithography (Mask 3): Pattern the metal layer to form the anode and cathode contacts and remove excess metal.

5.2 npn Bipolar Junction Transistor (BJT) Fabrication

This is a more complex process involving multiple doping steps to create the Collector, Base, and Emitter regions.

Process Flow:

1. Start: p-type substrate.
2. Buried Layer (Mask 1): Implant a low-resistivity n+ region (the "buried layer"). This reduces the collector series resistance.
3. Epitaxy: Grow a high-quality, lightly doped n-type silicon layer (the collector) over the entire wafer. The buried layer remains underneath it.
4. Isolation (Mask 2): Use diffusion or implantation to create deep p+ regions that extend from the surface down to the p-type substrate. This isolates adjacent npn transistors from each other.
5. Base Diffusion (Mask 3): Open a window in the oxide and introduce p-type dopants to form the base region within the n-type epitaxial layer.
6. Emitter Diffusion (Mask 4): Open a smaller window within the base region and introduce a high concentration of n-type dopants (n+) to form the emitter. A simultaneous n+ implant is often done in the collector region for a low-resistance contact.
7. Contact Cut (Mask 5): Open windows in the oxide for contacts to the Emitter, Base, and Collector.
8. Metallization (Mask 6): Deposit and pattern metal to connect to the E, B, and C terminals.

5.3 pnp Bipolar Junction Transistor (BJT) Fabrication

A pnp BJT can be fabricated alongside an npn BJT.

• Vertical pnp: Can be made using the p-substrate as the collector, the n-type epitaxial layer as the base, and a p-type diffusion (similar to the npn base step) as the emitter. Performance is generally poor.
• Lateral pnp: A more common structure where the emitter and collector are both p-type regions diffused into the n-type epitaxial layer (the base). Current flows laterally between them. This structure is easier to integrate into an npn process but has lower performance than a vertical npn.

5.4 MOSFET Fabrication

5.4.1 Enhancement-Mode MOSFET (n-MOS Example)

An n-channel enhancement-mode MOSFET is "normally off" and requires a positive gate voltage to turn "on."

Process Flow:

1. Start: p-type silicon substrate.
2. Well Formation (for CMOS): In a full CMOS process, this p-substrate would serve as the body for the n-MOS device.
3. Device Isolation: Create isolation regions (e.g., Shallow Trench Isolation - STI) to separate adjacent transistors.
4. Gate Oxidation: Grow a very thin, extremely high-quality layer of SiO₂. This is the critical gate dielectric.
5. Polysilicon Deposition: Deposit a layer of polycrystalline silicon (polysilicon) over the gate oxide. This will become the gate electrode.
6. Gate Patterning (Mask 1): Use lithography and etching to define the polysilicon gate.
7. Source/Drain Implantation: Use ion implantation to introduce n-type dopants (n+) into the silicon. The polysilicon gate itself acts as a mask, ensuring the source and drain regions are perfectly aligned to the gate (a "self-aligned" process).
8. Annealing: A high-temperature step to activate the implanted dopants and repair crystal damage. This also causes the dopants to diffuse slightly under the gate edges, ensuring good channel connection.
9. Dielectric Deposition: Deposit an insulating layer (e.g., SiO₂) over the entire wafer.
10. Contact Cut (Mask 2): Etch holes through the insulator to the Gate, Source, and Drain regions.
11. Metallization (Mask 3): Deposit and pattern metal to form the interconnects.

5.4.2 Depletion-Mode MOSFET (n-MOS Example)

A depletion-mode MOSFET is "normally on" and requires a negative gate voltage to turn "off." The fabrication is nearly identical to the enhancement-mode device, with one key additional step.

Key Difference:

• Channel Implant: Before the polysilicon gate is deposited, a low-dose n-type ion implantation is performed into the channel region. This creates a thin, conductive n-channel under the gate, even with zero gate voltage. All other steps are the same as for the enhancement-mode device.

5.5 CMOS Fabrication (Complementary MOS)

CMOS technology uses both n-MOS and p-MOS transistors together to create logic with very low static power consumption. The key challenge is to create both device types, which require opposite substrate polarities, on the same chip.

5.5.1 The CMOS Concept

• An n-MOS transistor is built in a p-type substrate/well.
• A p-MOS transistor is built in an n-type substrate/well.
• By connecting them in a complementary fashion (e.g., in an inverter), one transistor is always OFF in the steady state, preventing a direct path from power (VDD) to ground (GND) and thus consuming almost no power when not switching.

5.5.2 n-Well CMOS Process Flow (Inverter Example)

This process uses a p-type starting wafer and creates an "n-well" region to house the p-MOS transistor.

Process Flow:

1. Start: p-type substrate.
2. n-Well Formation (Mask 1): A mask protects the area where the n-MOS transistor will be built. N-type dopants are then implanted and diffused deep into the substrate to form the n-well for the p-MOS transistor.
3. Device Isolation (STI): Trenches are etched into the silicon, filled with oxide, and planarized. This electrically isolates the n-well from the p-substrate and separates all adjacent transistors.
4. Gate Oxidation: A thin gate oxide layer is grown over the entire wafer.
5. Polysilicon Deposition & Patterning (Mask 2): Polysilicon is deposited and etched to form the gates for both the n-MOS and p-MOS transistors simultaneously.
6. p-MOS Source/Drain Implant (Mask 3): The n-MOS region is covered with photoresist. P-type dopants (p+) are implanted to form the source and drain for the p-MOS transistor within the n-well. The polysilicon gate self-aligns these regions.
7. n-MOS Source/Drain Implant (Mask 4): The p-MOS region is now covered with photoresist. N-type dopants (n+) are implanted to form the source and drain for the n-MOS transistor within the p-substrate.
8. Annealing: Activate all dopants.
9. Contact Formation (Mask 5): An insulating dielectric is deposited, and contact holes are etched to all source, drain, and gate terminals.
10. Metallization (Mask 6): Metal is deposited and patterned to wire the transistors together. For an inverter, this involves:
    • Connecting the drains of both transistors together (output).
    • Connecting the gates of both transistors together (input).
    • Connecting the n-MOS source to Ground (GND).
    • Connecting the p-MOS source to Power (VDD).