Unit 6: Memory and Programmable Logic

Memory and programmable logic devices store binary information and implement logic functions in a reconfigurable fabric, replacing fixed gate networks with arrays that are either factory- or field-programmed. This section fixes the vocabulary the rest of the unit reuses.

• Memory word and capacity: a memory of 2^k × n holds 2^k words each n bits wide; k address lines select one word, n data lines carry it. A 1K × 8 chip needs 10 address lines and 8 data lines.
• Address decoding: an internal k-to-2^k decoder converts the address into a single active word line, enabling exactly one row.
• Volatility: volatile memory (RAM) loses contents on power-off; non-volatile memory (ROM) retains them.
• Programmable logic principle: any combinational function in sum-of-products form maps onto an AND array feeding an OR array; PLDs differ only in which array is programmable.
• Programmable connection symbol: a fuse/link at an array crossing is drawn as an × (intact) on a single input line into a gate, signalling a shared multi-input gate.

II. Read-Only Memory — Fixed and Field-Programmable Stores

A ROM is a decoder driving a programmable OR array: the k-to-2^k decoder generates all minterms of the address, and the connections in the OR plane fix each output bit.

A. Read-only memory

• Structure: 2^k word lines (all minterms) × n output columns; the AND array (decoder) is fixed, only the OR array is programmable.
• Truth-table realisation: each stored word is the OR-array pattern for that address, so a ROM directly tabulates any combinational function of k variables into n outputs.
• Programming technologies:
  • Mask ROM: connections defined at fabrication; lowest cost per unit at volume, non-alterable.
  • PROM: user blows fusible links once; one-time programmable.
  • EPROM: floating-gate charge erased by UV light; reprogrammable in bulk.
  • EEPROM / Flash: electrically erasable byte-wise or block-wise; basis of modern non-volatile storage.
• Worked mapping: to build a 3-bit-input circuit computing x², use a 8 × 6 ROM; address 011 (=3) stores 001001 (=9).

III. Read/Write Memory — SRAM and DRAM

Read/write memory (RAM) allows both storing and retrieving words during normal operation, using read/write control alongside address and data lines.

A. Read/Write memory

• Control lines: a Read/Write signal and a Chip Select (enable) gate transfers; when disabled the data lines float (high impedance).
• Timing: the access time is the delay from a valid address to valid output; the cycle time is the minimum interval between successive operations.
• Coincident selection: large arrays split the address into row and column decoders so a cell sits at the intersection, cutting decoder size from one k-to-2^k to two (k/2)-to-2^(k/2).

B. SRAM and DRAM

The two RAM families store a bit by opposed mechanisms, trading density against speed and simplicity.

1. Static RAM (SRAM):
   • Storage cell: a bistable latch of typically six transistors (cross-coupled inverters plus two access transistors).
   • Behaviour: holds its state as long as power is applied — no refresh needed.
   • Trade-off: fast access and simple interface, but low density and higher cost per bit; used for cache memory.
2. Dynamic RAM (DRAM):
   • Storage cell: a single transistor and a capacitor; charge present = 1, absent = 0.
   • Refresh requirement: capacitor charge leaks, so each row must be refreshed (read and rewritten) every few milliseconds.
   • Addressing: row and column addresses are time-multiplexed on shared pins using RAS (Row Address Strobe) and CAS (Column Address Strobe).
   • Trade-off: very high density and low cost per bit at the price of refresh overhead and slower access; used for main memory.

IV. PLAs and Their Applications — Dual Programmable Arrays

A Programmable Logic Array (PLA) has both the AND array and the OR array programmable, so it forms selected product terms and freely combines them, unlike the fixed-AND ROM.

A. Structure of the PLA

• Two planes: inputs (true and complemented) feed a programmable AND plane producing product terms; those product terms feed a programmable OR plane producing outputs.
• Size specification: given by inputs × product terms × outputs, e.g. a 16 × 48 × 8 PLA.
• Output polarity: an XOR gate at each output allows programmable inversion, so a function can be stored in its complemented form when that needs fewer product terms.
• Product-term sharing: a product term generated once can drive several outputs — the key economy over ROM.

B. PLAs and their applications

• Multi-output SOP logic: best where several functions share product terms, e.g. code converters and control decoders.
• Design procedure:
  • Minimise each output as SOP, minimising the total distinct product terms (not each function alone).
  • Choose true or complement output to reduce the term count further.
• PLA program table: columns list product terms against inputs (1/0/–) and outputs (1/–) with a T/C polarity column.
• Worked example: for F1 = AB + AC and F2 = AB + BC, the term AB is shared, so three product terms cover both outputs.
• Limitation: fixed number of product terms caps function complexity; unused terms waste silicon.

V. Sequential PLDs and Their Applications — Registered Programmable Logic

Sequential (registered) PLDs embed flip-flops after the programmable array so a single device realises both the combinational logic and the state storage of a finite-state machine.

A. Sequential PLDs and their applications

• Structure: an AND/OR array feeds a bank of D flip-flops; feedback from flip-flop outputs back into the AND array supplies the present-state variables.
• Macrocell: the configurable output block combining a flip-flop, an output-enable buffer, and a multiplexer selecting registered or combinational output.
  • Registered output: flip-flop Q drives the pin — for state and pipeline registers.
  • Combinational output: array output bypasses the flip-flop — for glue logic.
• State-machine mapping: next-state equations go into the array; the flip-flops hold the current state, so counters, sequencers and controllers fit in one chip.
• Device examples: the 22V10 GAL, with programmable macrocells and electrically erasable cells.
• Applications: address decoders with state, traffic-light and vending controllers, bus arbitration, and waveform generation.
• Design equations (Moore machine):

Next state:  Q(t+1) = f(inputs, Q(t))   -- in AND/OR array
Output:      Z       = g(Q(t))          -- from macrocell

Q(t) is present state fed back; f, g are the programmed SOP functions.

VI. Introduction to Field Programmable Gate Arrays — Reconfigurable Fabric

An FPGA is a large array of programmable logic blocks joined by programmable interconnect, configured in the field to implement complex digital systems far beyond the capacity of PLAs or PALs.

A. Introduction to field programmable gate arrays

• Configurable Logic Block (CLB): the repeating tile, built from look-up tables (LUTs) plus flip-flops.
  • Look-up table: a small SRAM that stores the truth table of a function; an n-input LUT holds 2^n bits and realises any function of n variables.
  • Flip-flop: registers the LUT output for sequential logic.
• Programmable interconnect: a matrix of routing channels and switch boxes wires CLBs together; configuration bits set the connections.
• I/O blocks: peripheral cells interfacing internal signals to package pins with programmable direction and standards.
• Configuration technology: most FPGAs are SRAM-based, so the bitstream loads at power-up from external non-volatile memory (volatile configuration); antifuse and flash variants exist.
• Design flow: HDL description → synthesis → place-and-route onto CLBs and routing → bitstream generation → download.
• Applications: prototyping ASICs, digital signal processing, custom accelerators, and hardware needing later field updates.

VII. PALs and Their Applications — Fixed-OR Programmable Logic

A Programmable Array Logic (PAL) device makes the AND array programmable but fixes the OR array, allocating a set number of product terms permanently to each output — the inverse trade-off to the PLA.

A. Structure of the PAL

• Fixed OR allocation: each output OR gate connects to a dedicated group of product terms (e.g. 3 or 4), which cannot be shared with other outputs.
• Feedback paths: many PAL outputs feed back into the AND array, enabling multi-level and registered logic.
• Naming convention: e.g. PAL16L8 — 16 inputs, 8 active-low outputs.

B. PALs and their applications

• Speed and simplicity: with only one programmable array, PALs are faster and cheaper than PLAs and easier to program.
• When suitable: functions where each output needs only a few product terms and little sharing — the common case in address decoding and glue logic.
• Comparison with PLA:
  1. PAL: programmable AND, fixed OR — faster, cannot share product terms across outputs.
  2. PLA: programmable AND and OR — more flexible via term sharing, but slower and costlier.
• Design constraint: if a function needs more product terms than the fixed OR gate allows, it must be factored, or a spare output used and fed back.
• Worked example: an output limited to 3 product terms cannot directly hold a 4-term function; one term is realised on a second output pin and fed back into the AND array to combine.
• Applications: memory-bank address decoders, bus interface logic, small state machines (registered PALs), and replacement of multiple 7400-series chips.