Unit 5: Sequential Logic Circuits Applications - Practice Quiz

1 A shift register is primarily used to perform which of the following operations?

2 How many basic types of shift registers are there based on data entry and exit modes?

3 In a SISO shift register, data is entered and taken out in which form?

4 A 4-bit SISO shift register requires how many clock pulses to shift in 4 bits of data?

5 Which shift register type loads all bits simultaneously and outputs them one bit at a time?

6 The basic building block of a shift register is a:

7 A bidirectional shift register can shift data in which direction(s)?

8 What controls the direction of shifting in a bidirectional shift register?

9 A universal shift register can perform which of the following operations?

10 Which component is typically used at the input of each stage of a universal shift register to select the operation?

11 In a synchronous counter, all flip-flops are clocked by:

12 An asynchronous counter is also commonly known as a:

13 Which counter is generally faster in operation?

14 How many flip-flops are needed to build a MOD-8 counter?

15 The maximum count of an -flip-flop binary counter is:

16 A ring counter is formed by connecting the output of a shift register back to its:

17 A 4-bit ring counter has how many valid states?

18 A 4-bit Johnson counter (twisted ring counter) has how many valid states?

19 In a Johnson counter, the feedback to the input comes from the:

20 Which counter provides a decoded output without needing extra decoding logic?

21 A 4-bit Serial-In Serial-Out (SISO) shift register is loaded with the data 1011 (MSB first). How many clock pulses are required to completely read out all 4 bits serially?

22 A Serial-In Parallel-Out (SIPO) shift register receives the serial input sequence 1, 0, 1, 1 on four successive clock pulses. If shifting is left-to-right, what parallel output () appears after the 4th pulse?

23 How many clock pulses does a 4-bit Parallel-In Serial-Out (PISO) register need to load data and then shift out all bits serially?

24 A ripple (asynchronous) up-counter uses 4 JK flip-flops, each with a propagation delay of . What is the maximum total propagation delay before the counter output is stable?

25 What is the key difference between a synchronous and an asynchronous counter?

26 A synchronous counter must count in the sequence (mod-10). What is the minimum number of flip-flops required?

27 A mod-6 asynchronous counter is built from a mod-8 (3 flip-flop) counter by resetting at a specific count. At which count should the RESET (via a NAND gate to CLEAR) be triggered?

28 For a 4-bit synchronous binary up-counter using T flip-flops, what should the T input of the third flip-flop () be?

29 A 4-bit ring counter is initialized to 1000. What is the maximum number of unique states (modulus) it cycles through?

30 A 4-bit Johnson (twisted-ring) counter produces how many unique states before repeating?

31 A Johnson counter is initialized to 0000. What is the state sequence for the first three clock pulses?

32 To design a mod-10 (decade) counter using the Johnson counter approach, how many flip-flops are needed?

33 Which statement correctly compares a ring counter and a Johnson counter with the same number () of flip-flops?

34 A shift register is used as a serial-to-parallel converter. If serial data arrives at into an 8-bit register, how often does a complete parallel byte become available?

35 Shifting a binary number left by one position in a shift register (with 0 fed in) is equivalent to what arithmetic operation?

36 A register holds the binary value 0110 (). After a single logical right shift (0 shifted into MSB), what value does it hold?

37 In a bidirectional shift register, what does the control (mode) input primarily determine?

38 A 4-bit bidirectional shift register holds 1001. With serial input 0 and the direction set to shift-right, what is the register content after one clock pulse?

39 A universal shift register (such as the 74194) typically uses two mode-select lines . Which operation corresponds to ?

40 Which combination of capabilities makes a shift register 'universal'?

41 A synchronous mod-6 counter is designed using T flip-flops. During the analysis, the designer finds that the unused states and must not lock the counter into an isolated loop. If the excitation for the MSB is , which additional design property guarantees a self-correcting counter?

42 A Johnson counter using flip-flops is used to generate timing signals. To decode any one of its unique states, how many inputs does each decoding AND gate require, and why?

43 A 4-bit SISO shift register is loaded serially with data (first bit entered = 1). After the fourth clock pulse, the register content (from MSB to LSB ) is:

44 A universal shift register (e.g., 74194) has mode-control inputs . Which combination performs synchronous parallel load of the register?

45 In a 4-bit asynchronous (ripple) up-counter with each flip-flop having propagation delay ns, the maximum worst-case output settling delay after a clock edge is:

46 A 4-bit bidirectional shift register shifts right when control and left when . If it currently holds and with serial left-input , what is the content after one clock?

47 A ring counter and a Johnson counter each use 5 flip-flops. What is the ratio of the number of distinct states (ring : Johnson)?

48 A synchronous counter is to be designed with the irregular sequence using JK flip-flops. How many flip-flops are minimally required?

49 For an -bit serial-in serial-out shift register operated at clock frequency , the time delay between serial input and serial output is:

50 In designing a synchronous mod-10 counter, the number of invalid (unused) states that must be considered for the design (using minimum flip-flops) is:

51 A 4-bit ring counter is initialized to . Due to a noise glitch, one extra 1 is injected, making the state . What is the resulting behavior of the (non-self-correcting) ring counter?

52 In a bidirectional shift register built from D flip-flops using 2-to-1 multiplexers at each stage, the total number of multiplexers required for an -bit register (supporting only left/right shift) is:

53 A synchronous counter uses the JK excitation , for its MSB. This effectively makes flip-flop behave as:

54 A universal shift register is used to implement a serial adder by recirculating data. To multiply an unsigned binary number by 2, the register should perform:

55 A self-decoding Johnson counter with 3 flip-flops produces how many uniquely decodable output states, and what is the maximum count frequency benefit over a binary counter of same size regarding decoding glitches?

56 A PIPO (parallel-in parallel-out) register differs from a PISO register primarily in that PIPO:

57 Consider a 4-bit synchronous up-counter using T flip-flops. The excitation input for the third flip-flop should be:

58 A bidirectional shift register is clocked at MHz. To rotate a 4-bit pattern completely around (end-around) and return to the original state in shift-left mode, the minimum time required is:

59 For a ripple counter to be converted to a mod-12 counter, a NAND gate resets all flip-flops when the count reaches 12. The NAND gate inputs must be connected to the outputs representing:

60 Two 4-bit universal shift registers are cascaded to form an 8-bit register. To shift the combined register right, the serial output of the higher-order register must feed: