Unit 5 - Practice Quiz

1 Which register is primarily used to configure the operation of Timer0 in PIC18 microcontrollers?

2 When Timer0 is configured in 16-bit mode, which pair of registers holds the count value?

3 What is the function of the prescaler in Timer0?

4 To turn on Timer0, which bit in the T0CON register must be set to 1?

5 Which register is used to control and configure Timer1 in a PIC18 microcontroller?

6 Timer1 is a 16-bit timer. Which two 8-bit registers are combined to store its value?

7 To use the internal instruction cycle clock () as the source for Timer1, what should the TMR1CS bit in the T1CON register be set to?

8 What is a primary difference between Timer1 and Timer0 in many PIC18 devices?

9 What is an Interrupt Service Routine (ISR)?

10 Which bit in the INTCON register must be set to enable all unmasked interrupts globally?

11 In a PIC18 microcontroller, what is an interrupt vector?

12 What is the purpose of an interrupt flag bit, such as TMR0IF?

13 To enable the Timer0 overflow interrupt, which two bits must be set?

14 When a Timer0 overflow interrupt occurs, which flag bit is set in the INTCON register?

15 What is a critical step that must be performed inside a timer's Interrupt Service Routine (ISR) before exiting?

16 To use the Timer1 overflow interrupt, which bit must be set in the PIE1 (Peripheral Interrupt Enable) register?

17 Which register contains the enable bit (INT0IE) and flag bit (INT0IF) for the external interrupt INT0?

18 What does an external hardware interrupt allow the microcontroller to do?

19 The INTEDG0 bit in the INTCON2 register is used to configure what aspect of the INT0 external interrupt?

20 After an external hardware interrupt is triggered and the processor jumps to the ISR, what must be done to the interrupt flag (e.g., INT0IF) before exiting the ISR?

21 A PIC18 is running with an oscillator frequency () of 20 MHz. What value should be loaded into the 8-bit TMR0 register to achieve a 1 ms delay using a 1:64 prescaler?

22 In a PIC18 microcontroller with interrupt priority enabled (IPEN=1), an external interrupt INT1 (configured as high priority) and a Timer0 overflow interrupt (configured as low priority) occur at the exact same time. Which Interrupt Service Routine (ISR) will be executed first?

23 To configure Timer1 on a PIC18 to operate as a 16-bit timer using the internal clock (), with a 1:8 prescaler, and to turn it on, which hexadecimal value should be written to the T1CON register?

24 After enabling the Timer0 interrupt (TMR0IE=1 and GIE=1) and configuring Timer0, what is the most critical action to perform inside the Timer0 Interrupt Service Routine (ISR) to prevent it from being continuously re-triggered?

25 You need to trigger an interrupt on the falling edge of a signal connected to the INT0 pin on a PIC18. Which register bit must be specifically configured for this purpose?

26 Consider the following C code for a PIC18: T0CON = 0b10000101;. What is the resulting configuration of Timer0?

27 What is the primary purpose of the PIE1 (Peripheral Interrupt Enable 1) register in a PIC18 microcontroller?

28 A PIC18 uses a 16 MHz crystal. To generate a delay of 50 ms using Timer1 in 16-bit mode with a 1:8 prescaler, what initial value should be loaded into the TMR1 register pair (TMR1H:TMR1L)?

29 In a PIC18 C program, you have an ISR defined as void __interrupt(low_priority) low_isr(void). Which register configuration is required for this ISR to handle a Timer1 overflow interrupt?

30 Why might a 100nF capacitor be placed between an external interrupt pin (e.g., INT0) and ground when the interrupt is triggered by a mechanical switch?

31 If Timer0 is configured in 8-bit mode with a 1:256 prescaler and an internal clock of , what is the maximum delay that can be generated in a single overflow cycle? Assume = 16 MHz.

32 What happens if a high-priority interrupt occurs while a low-priority ISR is already executing in a PIC18 (with IPEN=1)?

33 When using Timer1 as an asynchronous counter for external events (TMR1CS=1, T1SYNC=1), what is a major advantage of this mode?

34 Analyze the following PIC18 ISR code snippet. What is a potential issue with it? void __interrupt() my_isr(void) { if (PIR1bits.TMR1IF) { // Toggle an LED PORTBbits.RB0 = ~PORTBbits.RB0; // Reload Timer1 TMR1 = 0xC2F7; } }

35 To enable both the external interrupt on pin INT2 and the "interrupt-on-change" for PORTB (pins RB7:RB4), which combination of interrupt enable bits must be set?

36 A programmer wants to generate a time delay by polling the TMR0IF flag instead of using an interrupt. Which C code snippet correctly implements this blocking delay?

37 What are the memory addresses for the high-priority and low-priority interrupt vectors in a standard PIC18 microcontroller?

38 In a C program for a PIC18, how would you read the entire 16-bit value of a running Timer1 into an unsigned int variable named timer_value in a single, atomic operation provided by the XC8 compiler?

39 An application uses a Timer1 interrupt every 10ms to increment a counter. The main loop must perform an action every 1 second. What is the most robust and efficient way to implement this logic?

40 You have configured the INT0 external interrupt for a rising edge. In the ISR, you clear the INT0IF flag. However, the interrupt triggers again immediately upon exit. Assuming no switch bounce, what is a likely cause?

41 A PIC18F running at MHz is configured with Timer0 in 16-bit mode with a 1:64 prescaler. To generate a precise interrupt every 500 ms, an ISR reloads Timer0 with a value TMR0_PRELOAD and uses a software counter that triggers an event after N interrupts. Which combination of TMR0_PRELOAD and N achieves this target?

42 Consider the following PIC18 C code snippet intended to configure Timer0 in 16-bit mode.
c
T0CON = 0b00000011; // 16-bit, FOSC/4, Prescaler 1:16
TMR0H = 0x0B;
TMR0L = 0xDC;
T0CONbits.TMR0ON = 1;

According to the PIC18 datasheet, when writing to TMR0H, the value is held in a temporary register until TMR0L is written. What is the potential issue if a high-priority interrupt occurs between the TMR0H write and the TMR0L write, and the ISR also modifies Timer0?

43 A developer configures Timer0 as an 8-bit external event counter using the T0CKI pin. They set T0CON = 0b01101000;. However, they observe that the timer is not incrementing on events at T0CKI, but is instead incrementing at a rate related to the system clock. What is the most likely cause of this misbehavior?

44 Given T0CON = 0b10000101;, and a PIC18 running at MHz. The timer is running. At a certain point, a read of the 16-bit timer value is performed using this sequence: low_byte = TMR0L; high_byte = TMR0H;. What is a potential critical flaw in this reading method?

45 A PIC18 is configured with Timer1 in 16-bit Asynchronous Counter mode to count external events while the CPU is in SLEEP mode. The configuration is T1CON = 0b00000111;. The oscillator for Timer1 is a low-power 32.768 kHz watch crystal connected to T1OSI and T1OSO. What happens to the TMR1 register value if the main CPU is put to sleep using the SLEEP() instruction?

46 A scenario where Timer1 is used with the CCP module in Capture mode to measure the period of an incoming signal. Configuration: Timer1 is free-running, clocked by , with MHz. An engineer observes that for a high-frequency input signal, the captured values (CCPR1H:CCPR1L) occasionally seem to give a very large period measurement instead of a small one. What is the most plausible cause?

47 Timer1 is configured with T1CON = 0b10010001; and MHz. What is the maximum resolution (i.e., the time duration of a single timer tick) of Timer1 in this configuration, and what is its total overflow period if it starts from 0x0000?

48 A developer is using Timer1's Gate Control feature (T1GCON) to measure the width of a high pulse on the T1G pin. The configuration is: T1GCON = 0b10010001;, Timer1 is on and clocked internally. What does this specific T1GCON configuration imply about how the measurement is performed?

49 A PIC18 has interrupt priority enabled (IPEN = 1). A low-priority Timer0 interrupt (TMR0IP = 0) and a high-priority external interrupt (INT0IP = 1) have their flags set at the exact same time. The high-priority ISR for INT0 takes 20 instruction cycles. Global interrupts are enabled. What is the execution flow?

50 In a PIC18 system with interrupt priorities enabled (IPEN=1), an engineer writes a low-priority ISR. To ensure atomicity of a certain operation within this ISR, they decide to temporarily disable high-priority interrupts. What is the correct and safest way to achieve this inside the low-priority ISR?

51 A developer is debugging a PIC18 system. After a brown-out event, they find the device is stuck in a loop. Upon examining the RCON register, they find its value is 0b00001001. What can be concluded about the sequence of reset events?

52 A system has two active interrupts: a high-priority ADC interrupt (ADIP=1) and a low-priority UART receive interrupt (RCIP=0), with IPEN=1. The UART ISR is currently executing a critical section where it has temporarily disabled high-priority interrupts by clearing GIEH. During this critical section, an ADC conversion completes, setting the ADIF flag. What happens immediately after GIEH is set back to 1 at the end of the critical section?

53 In a PIC18 Timer0 ISR, the following C code is used to reload the timer. The system clock is MHz, Timer0 is in 8-bit mode with a 1:256 prescaler.
c
void interrupt tc_int(void) {
if (TMR0IF) {
// ... toggle LED ...
TMR0L = 100;
TMR0IF = 0;
}
}

What is the primary issue with this ISR code that will lead to significant cumulative timing error (jitter and drift)?

54 To create a software PWM signal, a developer uses a single Timer1 overflow interrupt. To achieve a 25% duty cycle on a 20ms period, the pin must be high for 5ms and low for 15ms. What is the most efficient and accurate interrupt-driven method?

55 A developer sets up Timer0 and Timer1 interrupts, with Timer0 as high priority and Timer1 as low priority (IPEN=1). Timer0 ISR takes 15 µs and interrupts every 25 µs. Timer1 ISR takes 40 µs and interrupts every 100 µs. At time t=0, both events occur. What percentage of CPU time is spent executing the main (non-interrupt) code? Assume no other tasks.

56 An external interrupt INT1 is configured as edge-triggered. The ISR for INT1 takes 50 µs to execute. The external signal connected to the INT1 pin is a square wave with a period of 40 µs (25 kHz frequency). What will be the observed behavior of the system?

57 A project uses Interrupt-on-Change for port B (RBIE). Pin RB4 is for a button input, and RB5 is an LED output controlled by writing to LATB in the main loop. The ISR is intended only for RB4. The ISR code is:
c
void interrupt low_priority isr(void) {
if (RBIF) {
if (PORTBbits.RB4 == 0) { / handle button / }
RBIF = 0; // Clear interrupt flag
}
}

Why might this ISR be triggered unexpectedly?

58 The INT0 external interrupt is configured with INTCONbits.INT0E = 1;, INTCONbits.INT0IF = 0;, and INTCON2bits.INTEDG0 = 0; (falling edge). The main program enters SLEEP mode. A single, clean 100 ns negative pulse occurs on the RB0/INT0 pin. The PIC's instruction cycle time is 250 ns ( MHz). What is the expected outcome?

59 In a PIC18 system using high-priority interrupts, what is the primary purpose of the RETFIE FAST instruction compared to the standard RETFIE?

60 A PIC18's INT0 interrupt is configured for a falling-edge trigger from a 1 kHz square wave. The INT0 ISR increments a 16-bit volatile integer count. The main loop toggles an LED and resets count to 0 when count >= 1000. The LED toggles approximately every 2 seconds instead of the expected 1 second. What is the most probable cause?