Unit 3: Field effect transistors - Practice Quiz

FET stands for Field Effect Transistor. It's a type of transistor that uses an electric field to control the flow of current.

A FET is a voltage-controlled device because the voltage applied to the gate terminal controls the current flowing between the source and drain.

FETs have a very high input impedance (typically in mega-ohms), which means they draw very little current from the input signal source. BJTs have a much lower input impedance.

FETs are generally less noisy than BJTs, making them a better choice for sensitive applications like pre-amplifiers and signal processing circuits.

A JFET (Junction Field Effect Transistor) has three terminals: the Gate, the Drain, and the Source.

The three terminals of a JFET are the Source (where charge carriers enter the channel), the Drain (where they leave), and the Gate (which controls the channel).

The name 'n-channel' JFET directly refers to the fact that the main current-carrying path, the channel, is constructed from n-type semiconductor material.

The gate-source PN junction in a JFET is reverse-biased. This creates a depletion region that extends into the channel, controlling its width and thus the flow of current.

MOSFET stands for Metal-Oxide-Semiconductor Field Effect Transistor. The 'Oxide' refers to the thin insulating layer of Silicon Dioxide () that separates the gate from the channel.

The Silicon Dioxide layer is an excellent electrical insulator. It prevents direct current flow between the metal gate and the semiconductor channel, resulting in an extremely high input impedance.

An enhancement-type MOSFET (E-MOSFET) does not have a physical channel initially. A channel must be induced (enhanced) by applying a gate-source voltage greater than the threshold voltage. Therefore, it is 'OFF' at .

MOSFETs are classified into two main types based on their operating principle: Depletion-type (which are normally ON) and Enhancement-type (which are normally OFF).

A depletion-type MOSFET has a built-in channel and is normally 'ON'. Applying a reverse-bias gate voltage depletes the channel (depletion mode), and applying a forward-bias gate voltage enhances it further (enhancement mode).

The output characteristics show how the output current (Drain Current, ) changes with the output voltage (Drain-Source Voltage, ) for a constant input voltage ().

The transfer characteristics show how the input voltage (Gate-Source Voltage, ) controls the output current (Drain Current, ). It essentially 'transfers' the input control to the output.

Pinch-off voltage () is the value of at which the depletion regions from the gate almost touch, 'pinching off' the channel. Beyond this point, the drain current saturates and remains almost constant.

The saturation region is the flat part of the output characteristic curves where the JFET acts like a constant current source. Here, remains nearly constant even if increases.

In the Ohmic or linear region, the JFET behaves like a voltage-controlled resistor. The drain current is directly proportional to the drain-source voltage for a given gate voltage.

An enhancement-type MOSFET requires a minimum gate-source voltage, known as the threshold voltage (), to form a conductive channel between the source and drain and allow current to flow.

In a p-channel JFET, the channel is made of p-type semiconductor material, where the majority charge carriers are positively charged 'holes'.

The high input impedance of a FET (due to the reverse-biased gate in JFET or insulated gate in MOSFET) prevents it from drawing significant current from the signal source. This is crucial for weak signals to avoid 'loading' the source, which would alter the signal's voltage. A BJT has a much lower input impedance (forward-biased base-emitter junction) and would draw more current, affecting the signal integrity.

In an N-channel JFET, the gate is P-type material. Making more negative increases the reverse bias across the P-N junction between the gate and the channel. This causes the depletion regions to widen (expand), constricting the conductive channel. A narrower channel has fewer charge carriers available for conduction, thereby increasing its resistance.

The Shockley equation for a JFET is . Here, mA and V. Substituting V: \n mA.

For an N-channel E-MOSFET, a conductive channel is induced only when the gate-source voltage is greater than the threshold voltage . Since the applied V is greater than the required V, a layer of electrons is attracted to the substrate region just below the gate oxide, forming a conductive n-type channel between the source and drain, thus turning the device ON.

MOSFETs have a simpler structure and smaller die area compared to BJTs. Being voltage-controlled devices, they draw negligible gate current, leading to lower static power consumption. These factors combined allow billions of MOSFETs to be fabricated on a single chip, leading to the high integration density required for modern microprocessors and memory chips.

In a P-channel JFET, the channel is made of p-type material and the gate is n-type. To decrease drain current, the channel must be constricted. This requires increasing the reverse bias on the gate-channel junction, which is achieved by applying a positive voltage to the n-type gate with respect to the p-type source (positive ). The pinch-off voltage () is the at which the channel is completely closed, so it is also positive for a P-channel JFET.

The Silicon Dioxide () layer is an excellent electrical insulator. In a MOSFET, it is placed between the metal gate terminal and the silicon substrate (channel region). This insulation prevents any DC current from flowing from the gate into the channel. The control action is purely electrostatic (field-effect), which gives the MOSFET its characteristic extremely high input impedance, typically in the range of to .

In the saturation region, the drain current of an E-MOSFET is given by the equation , where K is a device constant. The current is proportional to the square of the term . As increases, the value of increases quadratically, causing a corresponding quadratic increase in the drain current .

As increases, the reverse bias between the gate and the channel becomes larger near the drain end than the source end. This causes the depletion regions to become wedge-shaped, wider at the drain. When reaches (with ), the depletion regions are widest at the drain and nearly touch. This condition is called pinch-off. Further increases in do not significantly increase the drain current, and the JFET enters the saturation region.

The key structural difference is the presence of a channel at zero gate bias. A D-MOSFET is built with a narrow, diffused channel connecting the source and drain. This allows current to flow even with . An E-MOSFET has no such pre-existing channel; a channel must be electrically induced by applying a greater than the threshold voltage.

The JFET enters saturation when the drain-source voltage is large enough to cause pinch-off at the drain end. This condition occurs when the total reverse bias between the gate and the channel at the drain end, which is , equals the magnitude of the pinch-off voltage, . Since , the boundary condition is . For an n-channel device, this simplifies to .

A D-MOSFET can operate in two modes. When a negative is applied to an N-channel D-MOSFET, the negative gate voltage repels electrons from the pre-existing n-channel. This process 'depletes' the channel of charge carriers, making it narrower and increasing its resistance, thus reducing drain current. This is called the depletion mode of operation.

A MOSFET is an ideal choice for this application. Its gate is electrically isolated from the channel by a thin oxide layer, meaning it requires almost no DC current to maintain its state (ON or OFF). This provides excellent isolation between the control signal (at the gate) and the power circuit (source-drain). A BJT requires a continuous base current to stay ON, which violates the zero control current requirement.

The transfer characteristic is governed by the Shockley equation, . This is a second-degree equation (quadratic) relating and . Plotting this equation results in a parabolic curve that starts at (when ) and decreases to zero at .

Operating the gate-source junction with reverse bias ensures that only a very small leakage current flows into the gate. This results in a very high input impedance, which is a key advantage of FETs. The reverse bias creates a depletion region whose width can be modulated by the gate voltage, thereby controlling the conductivity of the channel. If the junction were forward-biased, it would conduct like a diode, drawing significant gate current and resulting in a very low input impedance.

Ideally, in the saturation region, should be independent of . However, as increases, the pinch-off point at the drain moves slightly towards the source. This reduces the effective length of the conductive channel. A shorter channel has less resistance, causing a slight increase in the drain current. This effect is known as channel length modulation, analogous to the Early effect in BJTs.

For a P-channel E-MOSFET, the gate must be made negative relative to the source to attract holes from the n-type substrate and form a p-type conductive channel. The device turns on only when is more negative than the threshold voltage. Since is -2 V, a voltage like -3 V or -4 V is required to induce the channel and allow current to flow.

In the ohmic (or triode) region, the drain current is approximately linearly proportional to the drain-source voltage for small values of . The resistance of the channel () can be controlled by varying the gate-source voltage . This allows the MOSFET to function as a resistor whose value is set by a control voltage, a useful feature in programmable filters and attenuators.

In a P-channel JFET, the channel is made of p-type semiconductor material, so the majority charge carriers are holes. By convention, the source is the terminal where charge carriers enter the channel, and the drain is where they leave. For a P-channel device, holes (positive charges) enter at the source and leave at the drain. Conventional current is the direction of flow of positive charge. Therefore, the conventional drain current flows from the source terminal into the device and out through the drain terminal. However, the external circuit current is usually shown flowing into the drain, meaning it flows from drain to source through the channel.

The N+ source and drain regions are diffused into a P-type substrate, forming two back-to-back p-n junctions. To prevent these junctions from becoming forward-biased and drawing unwanted current, the substrate must be kept at the most negative potential in the circuit. Connecting the substrate to the source terminal (which is often grounded or at the lowest voltage) ensures that the source-substrate junction has zero bias and the drain-substrate junction is always reverse-biased during normal operation.

At high frequencies, the gate-source () and gate-drain () capacitances become significant. In a common-source amplifier configuration, the Miller effect makes the effective input capacitance , where is the voltage gain (a large negative number). This large effective capacitance presents a low impedance path () to the input signal, effectively shunting it and reducing the high-impedance advantage.

This is known as the 'body effect'. A negative reverse-biases the source-substrate and drain-substrate p-n junctions further. This widens the depletion layer under the gate, meaning more positive charge is needed on the gate to induce the n-channel (achieve inversion). Consequently, the threshold voltage increases. The relationship is approximately , where is the body effect parameter.

Channel length modulation is modeled by the term , where . The output resistance in saturation is . We can approximate by finding the x-intercept of the tangent line. An easier way is to use the formula . Here, and . So, . Using the relation , we can use the average current . Then . The closest answer is 40V. Alternatively, using , solving gives , so .

The pinch-off voltage is the reverse bias required to make the depletion regions from the gates touch and close the channel. The width of the depletion region is inversely proportional to the square root of the doping concentration. However, the pinch-off voltage itself is directly proportional to the channel doping () and the square of the channel half-width (). The formula is . Increasing directly increases the magnitude of . A higher doping concentration means more charge per unit volume needs to be uncovered to create the depleting electric field, thus requiring a larger reverse voltage.

First, we differentiate the Shockley equation with respect to : . The maximum transconductance, , occurs at . Substituting into the expression for gives: . Note that for an n-channel JFET, is negative and is positive, so is a positive value.

In short-channel devices, the lateral electric field () becomes very large. Carrier velocity does not increase indefinitely with the field; it saturates at a maximum value, . When this happens, the drain current becomes limited by . Since the inversion charge density is proportional to , the drain current becomes approximately linearly proportional to , a significant deviation from the classical long-channel model where .

In the subthreshold (or weak inversion) region, the current flow is dominated by diffusion rather than drift. The relationship is given by . This exponential relationship means that the transistor can still provide gain and function as a switch at very low gate voltages, which is crucial for ultra-low-power designs. However, this same current is a source of static leakage power when the device is supposed to be 'off', a major challenge in modern IC design.

The reverse bias across the p-n gate junction determines the width of the depletion region. This bias is not uniform along the channel. At the source end, the reverse bias is . At the drain end, the reverse bias is . Since the JFET is in saturation, is positive and larger than , making significantly larger than . A larger reverse bias creates a wider depletion region. Therefore, the depletion region is much wider near the drain, causing the channel to be constricted or 'pinched off' at that point.

The drain current in a FET is proportional to carrier mobility (). As temperature increases, increased lattice scattering causes carrier mobility to decrease. This reduction in mobility leads to a decrease in drain current for a given set of terminal voltages. This effect counteracts the increase in current that might arise from other temperature-dependent factors (like a decrease in threshold voltage). In BJTs, the collector current is exponentially dependent on temperature (), creating a strong positive feedback loop that can lead to thermal runaway if not properly biased.

D-MOSFETs have a physical channel built in and can operate in two modes. Depletion mode occurs for negative (for n-channel), where the gate voltage depletes carriers from the channel, reducing current. Enhancement mode occurs for positive , where the gate voltage attracts additional carriers (electrons) into the channel, enhancing its conductivity. Since is positive, it operates in enhancement mode, and the drain current will be greater than (the current at ).

In the saturation region, the drain current is given by . We need to solve for .




V.
The condition for saturation is .
The minimum for saturation is V.

A JFET relies on the reverse-biased gate-source junction to achieve its high input impedance and to control the channel via the electric field of the depletion region. If this junction is forward-biased, it behaves like a forward-biased diode. A large gate current () will flow from the gate to the source. This effectively shorts the input, making the input impedance very low and negating the primary advantage of the FET. The gate voltage is no longer able to effectively modulate the channel resistance, and control over is lost.

The saturation drain current is . Since is directly proportional to the ratio, if , then . The transconductance in saturation is . Since is also directly proportional to the ratio, it follows that . An alternative expression is . Substituting and into this gives .

The on-state resistance in the triode region (for small ) is given by . To minimize , the term must be maximized. Power MOSFETs achieve extremely large effective values by creating a structure of thousands of small, parallel MOSFET cells on a single chip. This large effective width allows the device to carry high currents with minimal voltage drop and power loss (), which is critical for motor driving applications.

The gate of a MOSFET is electrically isolated from the channel by a very thin layer of silicon dioxide (). This layer provides the high input impedance but also acts as the dielectric of a capacitor. It is designed to withstand a certain maximum electric field. An ESD event can easily apply a voltage to the gate terminal that is far beyond its rated limit, causing a dielectric breakdown of the thin oxide. This creates a permanent short or a leaky path between the gate and the channel, destroying the device.

In a self-bias configuration, the gate is connected to ground through a resistor (), so the gate voltage is 0 V (since ). The source terminal is at a voltage . The gate-source voltage is therefore . This linear equation relates and based on the external circuit component (). The Q-point is found by solving this equation simultaneously with the device's nonlinear transfer equation, .

In a long-channel device, the channel potential is primarily controlled by the gate. In a short-channel device, the source and drain are close enough that their depletion regions can interact. As increases, the drain's depletion region expands and its electric field extends towards the source. This field effectively counteracts the gate's control and lowers the potential energy barrier that keeps electrons in the source. With a lower barrier, inversion can be achieved with a lower gate voltage, meaning the threshold voltage has effectively decreased.

There are two main effects of temperature on : 1) Threshold voltage () decreases with temperature, which tends to increase the overdrive voltage () and thus increase . 2) Carrier mobility () decreases with temperature due to lattice scattering, which tends to decrease . At low , the effect dominates, giving a positive temperature coefficient. At high , the mobility effect dominates, giving a negative temperature coefficient. The ZTC point is the specific crossover bias voltage () where these two opposing effects perfectly balance each other out, resulting in a drain current that is stable over a range of temperatures.

In a p-channel JFET, the channel is p-type material and the gate is n-type. The majority carriers are holes. To create a reverse bias at the gate junction to control the channel, the n-type gate must be made positive with respect to the p-type source; hence must be positive. To cause holes to flow from source to drain, the drain must be at a lower potential than the source; hence must be negative. The pinch-off voltage () for a p-channel device is the positive that cuts off the channel current. Therefore, for amplification, must be positive but less than .

In the triode region for small , the MOSFET behaves like a resistor. The drain current is given by . The resistance is . Therefore, is inversely proportional to the overdrive voltage, . If is doubled and is well above , the overdrive voltage approximately doubles. For example, if V and initial V, the overdrive is 3V. If is doubled to 8V, the new overdrive is 7V, which is slightly more than double. So will be slightly less than half of . The best approximation is .