Unit 6 - Notes

ECE249

Unit 6: Applications of Sequential Circuits

1. Introduction to Sequential Circuits

Unlike combinational circuits (where output depends only on present input), sequential circuits utilize a memory element. The output depends on the present inputs and the past outputs (history). The basic building block of a sequential circuit is the Flip-Flop.

2. Registers

A register is a group of flip-flops used to store or manipulate binary data. An $n$ -bit register consists of $n$ flip-flops and is capable of storing $n$ bits of information.

Shift Registers

A shift register is a sequential logic circuit capable of storing and transferring data. Data can be shifted to the left or right based on clock pulses.

A. Serial In - Serial Out (SISO)

Operation: Data is entered one bit at a time (serially) and retrieved one bit at a time.
Mechanism:
- Consists of cascaded D Flip-Flops.
- The output of one flip-flop is connected to the input of the next.
- For an $N$ -bit register, it takes $N$ clock pulses to load the data and another $N$ clock pulses to shift the data out.
Application: Used for temporary data storage and time delay generation.

B. Serial In - Parallel Out (SIPO)

Operation: Data is entered serially (one by one) but the outputs are taken from all flip-flops simultaneously (in parallel).
Mechanism:
- Data enters the first flip-flop.
- Once the register is full (after $N$ clock cycles), all outputs ( $Q_0, Q_1, ... Q_{n-1}$ ) are read at once.
Application: Serial-to-Parallel data conversion (essential in communication systems).

C. Parallel In - Serial Out (PISO)

Operation: Data is loaded onto the flip-flops simultaneously (in parallel) and shifted out one bit at a time.
Mechanism:
- Requires a control signal (usually labeled Shift/ $\overline{\text{Load}}$ ).
- Load Mode ($0$): Data is written to all flip-flops via combinational gates.
- Shift Mode ($1$): The circuit acts as a SISO register, shifting bits out on every clock pulse.
Application: Parallel-to-Serial conversion (e.g., sending data from a computer processor to a USB port).

D. Parallel In - Parallel Out (PIPO)

Operation: Data is loaded simultaneously and output simultaneously.
Mechanism:
- Does not shift data left or right.
- Upon a clock trigger, the inputs $D_0...D_n$ appear immediately at outputs $Q_0...Q_n$ .
- Requires only 1 clock pulse to load data.
Application: Temporary storage (Buffer registers) in CPUs.

3. Counters

A counter is a sequential circuit that goes through a prescribed sequence of states upon the application of input pulses.

Classification of Counters

Asynchronous (Ripple) Counters: The external clock is applied only to the first flip-flop. Subsequent flip-flops are clocked by the output of the previous flip-flop.
Synchronous Counters: A common clock is applied to all flip-flops simultaneously.

4. Asynchronous Counters (Ripple Counters)

Triggering: Generally uses T Flip-Flops or JK Flip-Flops (with $J=K=1$ ) in toggle mode.
Delay: Since the clock ripples through the stages, the propagation delay accumulates. This limits the maximum operating frequency.

A. Asynchronous UP Counter

Operation: Counts from $0$ to $2^n - 1$ .
Mechanism:
- The first Flip-Flop (LSB) is clocked by the external clock.
- Each subsequent Flip-Flop is clocked by the falling edge of the Normal Output ( $Q$ ) of the previous Flip-Flop.
- Example (3-bit): $Q_0$ toggles on every clock. $Q_1$ toggles when $Q_0$ goes $1 \to 0$ . $Q_2$ toggles when $Q_1$ goes $1 \to 0$ .

B. Asynchronous DOWN Counter

Operation: Counts from $2^n - 1$ down to $0$.
Mechanism:
- Similar to the UP counter, but the clock for the next stage is derived differently.
- Subsequent Flip-Flops are clocked by the falling edge of the Inverted Output ( $\bar{Q}$ ) of the previous Flip-Flop (or the rising edge of $Q$ ).

C. Asynchronous Mod-N Counter

Definition: A counter that counts through $N$ states (0 to $N-1$ ) and then resets.
Modulus (Mod): The number of states a counter counts. A standard 4-bit counter is Mod-16 (0–15).
Mechanism (Reset Logic):
- To create a Mod- $N$ counter (where $N < 2^n$ ), combinational logic (usually a NAND gate) is used to decode state $N$ .
- When the count reaches $N$ (binary), the NAND gate output goes LOW, triggering the active-low CLEAR (CLR) or RESET inputs of all flip-flops, forcing the count back to 0 immediately.
- Example (Mod-10 / BCD Counter): Counts 0–9. When it hits 10 (binary 1010), the logic detects $Q_3=1$ and $Q_1=1$ , resets the circuit to 0000.

5. Synchronous Counters

Triggering: All flip-flops receive the same clock pulse simultaneously.
Speed: Faster than asynchronous counters because there is no cumulative propagation delay.
Complexity: Requires more combinational logic (AND gates) to determine when a flip-flop should toggle.

A. Synchronous UP Counter

Logic: A flip-flop should toggle only if all preceding flip-flops are in the HIGH (1) state.
- $FF_0$ (LSB): Toggles on every clock ( $J=K=1$ ).
- $FF_1$ : Toggles if $Q_0 = 1$ .
- $FF_2$ : Toggles if $Q_0 = 1$ AND $Q_1 = 1$ .
- $FF_n$ : Toggles if $Q_0 \cdot Q_1 \cdot ... \cdot Q_{n-1} = 1$ .

B. Synchronous DOWN Counter

Logic: A flip-flop toggles only if all preceding flip-flops are in the LOW (0) state.
- Implemented by using the inverted outputs ( $\bar{Q}$ ) in the AND gate logic chain.
- $FF_1$ toggles if $\bar{Q}_0 = 1$ .

C. Synchronous Mod-N Counter

Design Process:
1. Determine the number of Flip-Flops ( $2^n \geq N$ ).
2. Draw the State Diagram (0 to $N-1$ ).
3. Create the Excitation Table for the specific Flip-Flop used (usually JK or T).
4. Use K-Maps to derive the simplified Boolean expressions for the flip-flop inputs.
5. The logic ensures that after state $N-1$ , the next state is 0. Unlike asynchronous counters, there is no "glitch" caused by a momentary reset; the transition to 0 happens cleanly on the clock edge.

6. Shift Register Counters (Special Counters)

These are synchronous counters formed by connecting the output of a shift register back to its input.

A. Ring Counter

A circular shift register.

Construction: Connect the output of the last flip-flop ( $Q_{last}$ ) directly to the input of the first flip-flop ( $D_{first}$ ).
Initialization: Requires a "Preset" to load an initial logical 1 into the first stage and 0s elsewhere (e.g., 1000).
Operation: On every clock pulse, the single "1" shifts to the next position.
- Sequence (4-bit): 1000 $\to$ 0100 $\to$ 0010 $\to$ 0001 $\to$ 1000...
Modulus: Mod- $N$ (where $N$ is the number of Flip-Flops).
States Used: $N$ states. (With 4 FFs, only 4 of the 16 possible states are used).
Usage: Used in stepper motor control and creating sequential timing pulses.

B. Johnson Ring Counter (Twisted Ring Counter)

A modification of the ring counter to double the number of states.

Construction: Connect the inverted output of the last flip-flop ( $\bar{Q}_{last}$ ) to the input of the first flip-flop ( $D_{first}$ ).
Initialization: Usually cleared to all 0s (0000).
Operation:
1. Initially 0000. $\bar{Q}_{last}$ is 1, so 1 enters the front.
2. Fills with 1s: 1000 $\to$ 1100 $\to$ 1110 $\to$ 1111.
3. Once full of 1s, $\bar{Q}_{last}$ becomes 0, so 0 enters the front.
4. Fills with 0s: 0111 $\to$ 0011 $\to$ 0001 $\to$ 0000.
Modulus: Mod- $2N$ . (A 4-bit Johnson counter has 8 distinct states).
States Used: $2N$ states.
Usage: Used for frequency division and generating multi-phase clock signals.

Comparison Table: Ring vs. Johnson

Feature	Ring Counter	Johnson Counter
Feedback	$Q_n \to D_0$ (Direct)	$\bar{Q}_n \to D_0$ (Inverted)
No. of States (Modulus)	$N$	$2N$
Used States (4-bit)	4	8
Decoding Logic	Simple (No gates required)	Requires gates to decode states