Unit 5: Introduction to Sequential Logic Circuits

1. Overview of Sequential Logic

Unlike combinational logic circuits, where the output depends solely on the current inputs, sequential logic circuits depend on both the current inputs and the past history of inputs (current state).

• Memory Element: The defining feature of sequential circuits is the presence of memory elements (feedback loops) that store binary information.
• Block Diagram: A sequential circuit consists of a combinational circuit and memory elements.
• State: The binary information stored in the memory elements at any given time defines the "state" of the sequential circuit.

2. Latches

A Latch is the most basic type of binary storage device. It is an asynchronous device (outputs can change state as soon as inputs change) and is level-triggered.

2.1 The S-R (Set-Reset) Latch

The SR Latch has two inputs, (Set) and (Reset), and two outputs, and (complement of ).

A. NOR Gate SR Latch (Active High)

Constructed using two cross-coupled NOR gates.

• No Change (Hold): . The output remains in its previous state ().
• Reset: . The output becomes 0.
• Set: . The output becomes 1.
• Invalid (Forbidden): . Both outputs try to go to 0, violating the rule that and must be complements.

Truth Table (NOR Latch):

B. NAND Gate SR Latch (Active Low)

Constructed using two cross-coupled NAND gates. The inputs are often labeled and because they are active low (a 0 triggers the action).

• Invalid: .
• Set: .
• Reset: .
• Hold: .

2.2 The Gated D (Data) Latch

To solve the "Invalid" state problem of the SR latch and to control when the state changes, the D Latch is used. It ensures and are never equal to 1 at the same time.

• Construction: Derived from an SR latch by adding an inverter between S and R input, creating a single input . An Enable ( or ) pin gates the input.
• Operation (Transparent Latch):
  • When Enable = 1: follows . (If ; if ).
  • When Enable = 0: The latch is disabled; it holds the previous value regardless of changes in .

3. Flip-Flops

Flip-flops are synchronous bistable devices. Unlike latches, they are edge-triggered. They sample inputs and change outputs only at a specific transition of the clock signal (either the rising edge or the falling edge).

3.1 SR Flip-Flop

The clocked SR flip-flop operates similarly to the SR latch but changes state only on the clock edge.

• Symbol Inputs: S, R, CLK.
• Outputs: .
• Problem: It still possesses the invalid state when and .

Characteristic Equation:

3.2 JK Flip-Flop

The JK Flip-Flop is the most versatile flip-flop. It solves the undefined state () of the SR flip-flop.

• Inputs: J (corresponds to Set), K (corresponds to Reset), CLK.
• Operation:
  • : Hold (No change).
  • : Reset ().
  • : Set ().
  • : Toggle. The output inverts ().

Characteristic Equation:

Truth Table:

3.3 D Flip-Flop (Delay Flip-Flop)

The D flip-flop transfers the data at input D to output Q on the clock edge.

• Usage: Used widely in digital electronics for data storage registers and counters.
• Operation:
  • If , becomes 0.
  • If , becomes 1.

Characteristic Equation:

3.4 T Flip-Flop (Toggle Flip-Flop)

A T flip-flop is a single-input version of the JK flip-flop where and are connected together ().

• Operation:
  • If : Hold ().
  • If : Toggle ().
• Usage: Frequency division and binary counters.

Characteristic Equation:

4. Master-Slave Flip-Flop

4.1 The Race-Around Condition

In a standard level-triggered JK flip-flop (or if the clock pulse is too wide), when , the output toggles. If the propagation delay of the flip-flop is less than the clock pulse width, the output may toggle multiple times within a single clock pulse. This leads to an indeterminate state known as the Race-Around Condition.

4.2 The Master-Slave Solution

The Master-Slave JK Flip-Flop eliminates the race-around condition by using two cascaded flip-flops driven by complementary clocks.

Construction:

1. Master Flip-Flop: Receives external inputs () and the Clock.
2. Slave Flip-Flop: Takes the output of the Master as its input. It receives an inverted Clock.

Working Principle:

• During Clock High (CLK = 1): The Master is active and processes inputs and . The Slave is inactive (disabled) because its clock is 0. The Slave holds the previous value.
• During Clock Low (CLK = 0): The Master becomes inactive (holds its state). The Slave becomes active, reads the Master's output, and passes it to the final output .
• Result: The output changes only once per clock cycle (on the falling edge of the clock), preventing the race-around condition.

5. Conversion of Basic Flip-Flops

Flip-flop conversion involves designing a combinational circuit to make one type of flip-flop (Available) behave like another type (Target).

5.1 The General Procedure

1. Identify the Target Flip-Flop (the one required) and the Available Flip-Flop (the one physically present).
2. Draw the Characteristic Table of the Target Flip-Flop.
3. Add columns for the Excitation Table of the Available Flip-Flop. Determine the required inputs for the available FF to achieve the target's next state.
4. Use K-Maps to derive Boolean expressions for the inputs of the Available FF in terms of the Target Inputs and Current State ().
5. Draw the logic diagram.

5.2 Reference: Excitation Tables

Used to determine required inputs to transition from .

5.3 Example: Conversion of SR to JK Flip-Flop

• Target: JK Flip-Flop (Inputs ).
• Available: SR Flip-Flop (Inputs ).

Step 1: Conversion Table

Step 2: K-Map Simplification

• For Input S: Map inputs for output .
  • Grouping leads to:
• For Input R: Map inputs for output .
  • Grouping leads to:

Step 3: Implementation

• Use two AND gates.
• AND Gate 1: Inputs and Connect to .
• AND Gate 2: Inputs and Connect to .
• The resulting circuit acts exactly like a JK Flip-Flop.