Unit 4 - Notes

ECE206 10 min read

Unit 4: Transistor Biasing and Thermal Stabilization

1. The Operating Point and Bias Stability

1.1 What is Biasing?

For a transistor to function as an amplifier, it must be operated in the active region. Biasing is the process of applying DC voltages to the transistor terminals to set up a fixed level of DC current and voltage, known as the Operating Point or Quiescent Point (Q-point). This ensures the transistor operates correctly when an AC signal is applied.

1.2 The DC Load Line and Operating Point (Q-point)

The DC load line is a graphical representation of all possible combinations of collector current ( $I_C$ ) and collector-emitter voltage ( $V_{CE}$ ) for a given amplifier circuit. It is a straight line drawn on the transistor's output characteristics.

Derivation: Consider a simple common-emitter circuit. Applying KVL to the collector-emitter loop gives:
$V_{CC} = I_C R_C + V_{CE}$
$I_C = -\frac{1}{R_C}V_{CE} + \frac{V_{CC}}{R_C}$
This is the equation of a straight line (y = mx + c).
Endpoints of the Load Line:
1. Saturation Point (Max $I_C$ ): When $V_{CE} = 0$ (transistor is fully ON), the collector current is maximum.
  $I_{C(sat)} = \frac{V_{CC}}{R_C}$
2. Cutoff Point (Max $V_{CE}$ ): When $I_C = 0$ (transistor is fully OFF), the collector-emitter voltage is maximum.
  $V_{CE(cutoff)} = V_{CC}$
Q-point: The Q-point is the specific point on the DC load line that represents the DC values ( $I_{CQ}$ , $V_{CEQ}$ ) when no AC signal is applied. For best amplification without distortion, the Q-point is typically set near the middle of the load line.

1.3 Bias Stability

The Q-point is sensitive to changes in three main factors:

Temperature: An increase in temperature increases the reverse saturation current ( $I_{CO}$ ), which in turn increases the collector current ( $I_C$ ). It also decreases the base-emitter voltage ( $V_{BE}$ ).
Transistor Beta ( $\beta$ or $h_{FE}$ ): The value of $\beta$ varies significantly from one transistor to another, even for the same part number. It is also temperature-dependent.
Component Tolerances: The values of biasing resistors can vary.

Bias stability refers to the ability of a biasing circuit to keep the Q-point fixed despite variations in these parameters. A stable circuit maintains a nearly constant $I_{CQ}$ and $V_{CEQ}$ .

1.4 Stability Factors

To measure the stability of a biasing circuit, we use stability factors. A smaller stability factor indicates a more stable circuit.

Stability Factor, S: Measures the change in collector current ( $I_C$ ) with respect to the reverse saturation current ( $I_{CO}$ ).
$S = \frac{\partial I_C}{\partial I_{CO}}$
The general expression for S is: $S = \frac{1+\beta}{1-\beta(\frac{\partial I_B}{\partial I_C})}$
A smaller S (closer to 1) is desirable.
Stability Factor, S': Measures the change in $I_C$ with respect to the base-emitter voltage ( $V_{BE}$ ).
$S' = \frac{\partial I_C}{\partial V_{BE}}$
A smaller S' (more negative) is desirable.
Stability Factor, S'': Measures the change in $I_C$ with respect to the current gain ( $\beta$ ).
$S'' = \frac{\partial I_C}{\partial \beta}$
A smaller S'' is desirable.

2. Biasing Circuits

2.1 Fixed Bias (Not covered in list, but a baseline)

Description: A single resistor ( $R_B$ ) is connected between $V_{CC}$ and the base.
Analysis: $I_B = \frac{V_{CC} - V_{BE}}{R_B}$ . $I_C = \beta I_B$ .
Stability: Highly unstable. $S = 1 + \beta$ . A very large value, making the Q-point extremely dependent on $\beta$ . Not used in practice.

2.2 Collector to Base Bias (Collector Feedback Bias)

Description: The base resistor ( $R_B$ ) is connected from the collector to the base, providing feedback from the output to the input.
Circuit Diagram:
Q-point Analysis:
- Input Loop (KVL):
  $V_{CC} = (I_B + I_C)R_C + I_B R_B + V_{BE}$
  Since $I_C = \beta I_B$ , we can write $I_C \approx (\beta+1)I_B$ .
  $V_{CC} - V_{BE} = I_B(R_B + (\beta+1)R_C)$
  $I_B = \frac{V_{CC} - V_{BE}}{R_B + (\beta+1)R_C}$
- Collector Current:
  $I_{CQ} = \beta I_B = \frac{\beta(V_{CC} - V_{BE})}{R_B + (\beta+1)R_C}$
- Output Loop (KVL):
  $V_{CEQ} = V_{CC} - (I_B + I_C)R_C \approx V_{CC} - I_C R_C$
Stability:
- Mechanism: If $I_C$ tries to increase (due to temperature or $\beta$ change), the voltage drop across $R_C$ increases. This lowers the collector voltage $V_C$ . Since $V_C$ is connected to $R_B$ , the lower $V_C$ reduces the base current $I_B$ . The reduction in $I_B$ counteracts the initial increase in $I_C$ . This is negative feedback.
- Stability Factor (S): $S = \frac{1+\beta}{1+\frac{\beta R_C}{R_C+R_B}}$ . This value is less than $(1+\beta)$ , showing improved stability over Fixed Bias.
- Advantages: Better stability than fixed bias. Simple circuit.
- Disadvantages: AC gain is reduced due to feedback. Stability is only moderate.

2.3 Emitter Feedback Bias and Collector Emitter Feedback Bias

2.3.1 Emitter Feedback Bias

Description: Similar to fixed bias, but with an emitter resistor ( $R_E$ ) added.
Circuit Diagram:
Q-point Analysis:
- Input Loop (KVL):
  $V_{CC} = I_B R_B + V_{BE} + I_E R_E$
  Since $I_E = (\beta+1)I_B$ :
  $V_{CC} - V_{BE} = I_B R_B + (\beta+1)I_B R_E = I_B(R_B + (\beta+1)R_E)$
  $I_B = \frac{V_{CC} - V_{BE}}{R_B + (\beta+1)R_E}$
- Collector Current:
  $I_{CQ} = \beta I_B = \frac{\beta(V_{CC} - V_{BE})}{R_B + (\beta+1)R_E}$
- Output Loop (KVL):
  $V_{CEQ} = V_{CC} - I_C R_C - I_E R_E \approx V_{CC} - I_C(R_C + R_E)$
Stability:
- Mechanism: If $I_C$ increases, $I_E$ also increases. This increases the voltage drop across $R_E$ ( $V_E = I_E R_E$ ). Since $V_B$ is relatively fixed, the base-emitter voltage $V_{BE} = V_B - V_E$ decreases. A lower $V_{BE}$ reduces $I_B$ , which in turn counteracts the increase in $I_C$ .
- Stability Factor (S): $S = \frac{1+\beta}{1+\frac{\beta R_E}{R_B+R_E}}$ . Again, an improvement over fixed bias.

2.3.2 Collector-Emitter Feedback Bias

Description: This is a combination of the previous two, with feedback from the collector via $R_B$ and an emitter resistor $R_E$ .
Analysis: The analysis combines the KVL equations from both circuits, leading to more complex but more stable results.
Stability: It offers better stability than either Collector Feedback or Emitter Feedback bias alone.

2.4 Self Bias (Voltage Divider Bias)

This is the most widely used biasing circuit due to its excellent stability.

Description: The base voltage is set by a voltage divider network consisting of resistors $R_1$ and $R_2$ . An emitter resistor $R_E$ provides stabilization.
Circuit Diagram:

2.4.1 Exact Analysis (Thevenin's Theorem)

Simplify the base circuit: The voltage divider ( $V_{CC}$ , $R_1$ , $R_2$ ) can be replaced by its Thevenin equivalent.
- Thevenin Voltage ( $V_{TH}$ ): This is the open-circuit voltage at the base.
  $V_{TH} = V_B = V_{CC} \frac{R_2}{R_1 + R_2}$
- Thevenin Resistance ( $R_{TH}$ ): This is the resistance looking back into the base terminal with $V_{CC}$ grounded.
  $R_{TH} = R_1 || R_2 = \frac{R_1 R_2}{R_1 + R_2}$
Analyze the simplified circuit:
- Input Loop (KVL): Applying KVL to the simplified base-emitter loop:
  $V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$
  Using $I_E = (\beta+1)I_B$ :
  $V_{TH} - V_{BE} = I_B R_{TH} + (\beta+1)I_B R_E = I_B(R_{TH} + (\beta+1)R_E)$
  $I_B = \frac{V_{TH} - V_{BE}}{R_{TH} + (\beta+1)R_E}$
- Collector Current:
  $I_{CQ} = \beta I_B = \frac{\beta(V_{TH} - V_{BE})}{R_{TH} + (\beta+1)R_E}$
- Output Loop (KVL):
  $V_{CEQ} = V_{CC} - I_C R_C - I_E R_E \approx V_{CC} - I_C(R_C + R_E)$

2.4.2 Approximate Analysis

Condition for approximation: The circuit can be designed so that the base current ( $I_B$ ) is very small compared to the current flowing through the divider resistor $R_2$ ( $I_2$ ). This makes the base voltage $V_B$ almost independent of the transistor characteristics. The rule of thumb is:
If $\beta R_E \ge 10 R_2$ , we can use the approximate method.
Analysis:
1. Base Voltage: Since $I_B$ is negligible, the voltage divider is considered "stiff" or unloaded.
  $V_B \approx V_{TH} = V_{CC} \frac{R_2}{R_1 + R_2}$
2. Emitter Voltage:
  $V_E = V_B - V_{BE}$
3. Emitter and Collector Current:
  $I_E = \frac{V_E}{R_E} = \frac{V_B - V_{BE}}{R_E}$
  Since $I_C \approx I_E$ :
  $I_{CQ} \approx \frac{V_B - V_{BE}}{R_E}$
Note: In this approximation, $I_C$ is almost independent of $\beta$ , which is the key to this circuit's excellent stability.

3. Stabilization against Variations in VBE and Beta (for Self Bias)

Let's derive the stability factors for the Voltage Divider Bias circuit to mathematically prove its stability.

From the exact analysis, we have:
$I_C = \frac{\beta(V_{TH} - V_{BE})}{R_{TH} + (\beta+1)R_E}$
And since $I_E = I_C + I_B = I_C + I_C/\beta = I_C(1+1/\beta)$ , we can write the input loop KVL as:
$V_{TH} = \frac{I_C}{\beta} R_{TH} + V_{BE} + \frac{(\beta+1)}{\beta}I_C R_E$
$V_{TH} - V_{BE} = I_C (\frac{R_{TH}}{\beta} + \frac{(\beta+1)}{\beta}R_E)$
$I_C = \frac{V_{TH} - V_{BE}}{R_E + \frac{R_{TH}}{\beta+1}}$ (using $I_E = I_C(1+1/\beta)$ and $I_E = I_B(\beta+1)$ )

A more general expression for $I_C$ considering $I_{CO}$ is:
$I_C = \frac{\beta(V_{TH} - V_{BE}) + (R_{TH}+R_E)(1+\beta)I_{CO}}{R_{TH} + (1+\beta)R_E}$

3.1 Stability Factor (S)

$S = \frac{\partial I_C}{\partial I_{CO}} = \frac{(R_{TH}+R_E)(1+\beta)}{R_{TH} + (1+\beta)R_E} = (1+\beta)\frac{1+\frac{R_{TH}}{R_E}}{1+\beta + \frac{R_{TH}}{R_E}}$
If we design the circuit such that $R_{TH}/R_E \ll (1+\beta)$ (which is almost always true), then:
$S \approx \frac{1+\frac{R_{TH}}{R_E}}{1+\frac{R_{TH}}{(\beta+1)R_E}} \approx 1 + \frac{R_{TH}}{R_E}$

Conclusion: To get a small S (close to 1), we need $R_{TH}/R_E$ to be small. This means a small $R_{TH}$ (low values for $R_1, R_2$ ) and a large $R_E$ . This confirms the design principles for a stable circuit.

3.2 Stability Factor (S')

$S' = \frac{\partial I_C}{\partial V_{BE}} = \frac{-\beta}{R_{TH} + (1+\beta)R_E}$
Approximating for large $\beta$ :
$S' \approx \frac{-\beta}{\beta R_E} = -\frac{1}{R_E}$

Conclusion: A larger $R_E$ leads to a smaller magnitude of S', improving stability against $V_{BE}$ variations.

3.3 Stability Factor (S'')

$S'' = \frac{\partial I_C}{\partial \beta} = \frac{I_C}{\beta} \frac{1+\frac{R_{TH}}{R_E}}{1+\beta+\frac{R_{TH}}{R_E}}$

Conclusion: S'' is proportional to $I_C/\beta$ . A smaller $I_C$ and a stable design (small $R_{TH}/R_E$ ) lead to better stability against $\beta$ variations.

4. General Remarks on Collector Current Stability

Biasing Circuit	Stability Factor (S)	Stability Performance	Comments
Fixed Bias	$1+\beta$	Very Poor	Q-point is highly dependent on $\beta$ . Thermally unstable.
Collector Feedback Bias	$<\ (1+\beta)$	Fair	Simple to implement, provides moderate stability through negative feedback.
Emitter Feedback Bias	$<\ (1+\beta)$	Fair to Good	The emitter resistor provides good stability.
Voltage Divider (Self) Bias	$1 + \frac{R_{TH}}{R_E}$	Excellent	By making $R_E$ large and $R_{TH}$ small, S can be made close to 1.

5. Thermistor and Sensistor Compensation

These are compensation techniques that use temperature-sensitive devices to counteract the temperature-induced changes in $I_C$ .

5.1 Thermistor Compensation

Thermistor: A resistor whose resistance changes significantly with temperature. NTC (Negative Temperature Coefficient) thermistors are commonly used for bias compensation. For an NTC thermistor, resistance decreases as temperature increases.
Implementation: An NTC thermistor ( $R_T$ ) is connected in parallel with the lower voltage divider resistor ( $R_2$ ).
Mechanism:
1. Temperature increases.
2. This would normally cause $I_C$ to increase.
3. The resistance of the NTC thermistor ( $R_T$ ) decreases.
4. The equivalent resistance of ( $R_2 || R_T$ ) decreases.
5. This lowers the base voltage $V_B = V_{CC} \frac{(R_2||R_T)}{R_1 + (R_2||R_T)}$ .
6. The lower $V_B$ reduces the forward bias, decreasing $I_B$ and thus counteracting the initial rise in $I_C$ .

5.2 Sensistor Compensation

Sensistor: A heavily doped semiconductor that acts as a resistor with a Positive Temperature Coefficient (PTC). Its resistance increases as temperature increases.
Implementation: A sensistor is placed in the emitter leg (in series with $R_E$ ) or in the upper part of the voltage divider (in series with $R_1$ ).
Mechanism (in emitter leg):
1. Temperature increases.
2. Resistance of the sensistor ( $R_S$ ) increases.
3. The total emitter resistance ( $R_E' = R_E + R_S$ ) increases.
4. Since $I_E \approx (V_B - V_{BE})/R_E'$ , the larger $R_E'$ causes $I_E$ (and $I_C$ ) to decrease, counteracting the temperature-induced increase.

6. Thermal Runaway and Thermal Stability

6.1 Thermal Runaway

Thermal runaway is a destructive positive feedback phenomenon that can destroy a BJT.

The Vicious Cycle:
1. An increase in temperature ( $T_J$ ) causes the minority carrier current ( $I_{CO}$ ) to increase.
2. The increase in $I_{CO}$ causes the total collector current ( $I_C = \beta I_B + (\beta+1)I_{CO}$ ) to increase significantly.
3. The power dissipated at the collector junction ( $P_D = V_{CE} I_C$ ) increases.
4. This increased power dissipation heats up the junction, further increasing its temperature ( $T_J$ ).
5. This leads back to step 1, and the cycle repeats, causing $I_C$ and $T_J$ to spiral upwards until the transistor is destroyed.

6.2 Condition for Thermal Stability

To prevent thermal runaway, the rate at which heat is removed from the junction must be greater than the rate at which it is generated.

$P_D$ = Power dissipated at the collector junction.
$T_J$ = Junction temperature.
$T_A$ = Ambient temperature.
$\theta$ = Thermal resistance (°C/W) from junction to ambient.

The relationship is: $T_J - T_A = \theta P_D$

For stability, the rate of increase of power dissipation with respect to junction temperature must be less than the rate of heat removal.
The condition to prevent thermal runaway is:
$\frac{\partial P_D}{\partial T_J} < \frac{1}{\theta}$

In a self-bias circuit, the presence of $R_E$ causes $V_{CE}$ to decrease as $I_C$ increases ( $V_{CE} = V_{CC} - I_C(R_C+R_E)$ ). This reduction in $V_{CE}$ helps limit the increase in power dissipation ( $P_D = V_{CE}I_C$ ), making the circuit inherently resistant to thermal runaway. For stability, the Q-point should be chosen such that:
$V_{CEQ} < \frac{V_{CC}}{2}$

7. Bias Compensation (Diode Compensation)

This technique specifically compensates for changes in $V_{BE}$ due to temperature.

Problem: $V_{BE}$ decreases by approximately 2.5 mV/°C. This change can alter the Q-point.
Solution: Place a forward-biased diode in the emitter circuit or the base circuit. The diode's forward voltage ( $V_D$ ) has a similar temperature coefficient to the transistor's $V_{BE}$ .
Implementation (Diode in Emitter):
- Place a diode in the base circuit of a voltage divider bias configuration.
- The voltage at the base is $V_B$ . The KVL equation is $V_B = I_B R_{TH} + V_{BE} + V_D$ .
Implementation (Diode in Emitter Circuit for $V_{BE}$ ):
- In a voltage divider bias circuit, the emitter current is $I_E = (V_B - V_{BE}) / R_E$ .
- A diode (D) is placed in the base circuit, such that its voltage drop opposes $V_{BE}$ .
- Applying KVL to the base circuit of a voltage divider: $V_{TH} = V_{BE} + I_E R_E$ .
- If we place a diode such that $V_{TH}$ is derived from a network including a diode, $V_{TH}$ itself can be made to vary with temperature, canceling the change in $V_{BE}$ .
- A more common method is to use a current mirror configuration with a matched transistor acting as a diode, which provides excellent tracking.

8. Understanding Transistor Datasheets

Datasheets provide critical information for circuit design. Let's look at some common BJT transistors.

Key Parameter Groups:

Absolute Maximum Ratings: Exceeding these values may permanently damage the device.
Thermal Characteristics: Relate to power dissipation and temperature.
Electrical Characteristics: Define the transistor's behavior under specified conditions.

Example Transistors:

BC547 / BC548: General-purpose NPN transistors. BC548 has a lower voltage rating than BC547.
BC557 / BC558: PNP complements to BC547/BC548.
BC107: Older general-purpose NPN transistor in a metal can package (TO-18).

Summary of Key Parameters (Typical Values)

Parameter	Symbol	BC547	BC557 (PNP)	BC107	Description
Absolute Maximum Ratings
Collector-Emitter Voltage (Base open)	$V_{CEO}$	45 V	-45 V	45 V	Maximum voltage between C and E when the base is not connected.
Collector-Base Voltage (Emitter open)	$V_{CBO}$	50 V	-50 V	50 V	Maximum voltage between C and B.
Emitter-Base Voltage (Collector open)	$V_{EBO}$	6 V	-5 V	6 V	Maximum reverse voltage on the B-E junction.
Continuous Collector Current	$I_C$	100 mA	-100 mA	100 mA	Maximum DC current the collector can handle.
Total Power Dissipation (@ 25°C)	$P_{tot}$	500 mW	500 mW	300 mW	Maximum power the device can dissipate.
Electrical Characteristics
DC Current Gain	$h_{FE}$	110-800 (Grouped)	110-800 (Grouped)	110-450 (Grouped)	The value of $\beta$ . It has a very wide range and is often grouped (A, B, C).
Collector-Emitter Saturation Voltage	$V_{CE(sat)}$	< 250 mV @ 100mA	< -650 mV @ -100mA	< 250 mV @ 100mA	Voltage drop across C-E when the transistor is fully ON (saturated).
Base-Emitter ON Voltage	$V_{BE(on)}$	0.55 - 0.7 V	-0.6 to -0.75 V	~0.65 V	The forward voltage drop of the B-E junction.
Transition Frequency	$f_T$	300 MHz (typ)	150 MHz (typ)	150 MHz (typ)	The frequency at which the AC current gain drops to 1. Indicates high-freq performance.

9. Introduction to PSpice

9.1 What is PSpice?

PSpice (Personal Simulation Program with Integrated Circuit Emphasis) is a powerful software tool used by engineers to simulate and analyze the behavior of electronic circuits. It allows you to:

Build a virtual circuit.
Apply stimuli (DC voltages, AC signals).
Perform various types of analyses without needing physical components.
Measure voltages, currents, and power throughout the circuit.

9.2 Types of Analysis

DC Operating Point (.OP): Calculates the DC voltages and currents of the circuit (the Q-point). This is the most relevant analysis for transistor biasing.
DC Sweep: Sweeps a DC source through a range of values and plots circuit variables.
AC Sweep/Frequency Response: Analyzes the circuit's behavior over a range of frequencies.
Transient Analysis (.TRAN): Analyzes the circuit's behavior over time, useful for observing waveforms.

9.3 Basic PSpice Workflow

Schematic Capture: Draw the circuit using a graphical editor (like OrCAD Capture). You select components (resistors, capacitors, transistors like QBC547, sources like VDC) from libraries and wire them together.
Create Simulation Profile: Define the type of analysis you want to run (e.g., "Bias Point" for DC operating point).
Run Simulation: The simulator solves the circuit equations based on the component models.
View Results: The results are displayed. For a Bias Point analysis, voltages at each node and currents through each component are shown directly on the schematic or in an output file.

9.4 PSpice Netlist Example

A netlist is a text description of a circuit. It's the core input to the SPICE engine. Here is a netlist for the Voltage Divider Bias circuit discussed earlier.

Circuit to be simulated:

VCC = 12V
R1 = 39kΩ
R2 = 3.9kΩ
RC = 1kΩ
RE = 470Ω
Transistor = BC547B

PSPICE

* PSpice Netlist for Voltage Divider Bias Analysis

* --- Component Declarations ---
* Node 0 is ground
VCC     1   0   DC 12V      ; 12V DC source connected between node 1 and ground
R1      1   2   39k         ; Resistor R1 between node 1 (VCC) and node 2 (Base)
R2      2   0   3.9k        ; Resistor R2 between node 2 (Base) and ground
RC      1   3   1k          ; Resistor RC between node 1 (VCC) and node 3 (Collector)
RE      4   0   470         ; Resistor RE between node 4 (Emitter) and ground

* Transistor Q1: Collector=3, Base=2, Emitter=4
Q1      3   2   4   QBC547B   ; BJT model named QBC547B

* --- Model Definition ---
* This defines the parameters for the BC547B transistor model
.model QBC547B NPN(Is=1.8e-14 Vaf=100 Bf=290 Ikf=0.09 Ise=1.8e-12 Ne=1.5 Br=4)

* --- Analysis Command ---
* .OP tells PSpice to perform a DC Operating Point analysis
.OP

.END

Running this simulation would produce an output file with:

Voltages at nodes 1, 2, 3, and 4.
Currents through all components.
The Q-point parameters for the transistor Q1, such as $I_B$ , $I_C$ , $V_{BE}$ , and $V_{CE}$ . This allows you to verify hand calculations and analyze the stability of your design.

Unit 3

Unit 5