Unit6 - Subjective Questions

Basic Op-Amp Comparator:
A comparator is a circuit that compares a signal voltage applied at one input of an op-amp with a known reference voltage at the other input. It produces an output of either high or low saturation voltage ( or ), depending on which input is higher.

Operation:

• If the non-inverting input voltage () is greater than the inverting input voltage (), the output goes to positive saturation ().
• If , the output goes to negative saturation ().
• Mathematically: , where is the open-loop gain (ideally infinite).

Differences from Standard Amplifier:

1. Feedback: Amplifiers use negative feedback to control gain; comparators operate in an open-loop configuration (no feedback) or positive feedback.
2. Output: Amplifier outputs are linear reproductions of the input; comparator outputs are non-linear, toggling between saturation limits.
3. Application: Amplifiers condition signals; comparators are used for decision-making and digitizing signals.

Zero Crossing Detector (ZCD):
A Zero Crossing Detector is an application of a comparator where the reference voltage () is set to zero volts (). It detects when the input AC signal crosses the zero-voltage level and changes its output state accordingly.

Circuit Description:

• In a non-inverting ZCD, the input signal is applied to the non-inverting terminal (+), and the inverting terminal (-) is grounded ().
• When , the output is .
• When , the output is .
• It effectively converts a sinusoidal input signal into a square wave output.

Waveforms:

• Input: A continuous sine wave crossing the zero axis.
• Output: A square wave that switches from to at the exact moment the sine wave goes from negative to positive, and vice versa.

Applications: Phase meters, frequency counters, and timing circuits.

Schmitt Trigger:
A Schmitt trigger is a comparator circuit with positive feedback. It converts an irregular or noisy waveform into a sharp square wave or pulse. The positive feedback creates two distinct threshold voltage levels: the Upper Threshold Point (UTP) and the Lower Threshold Point (LTP).

Operation:

• When the input voltage exceeds the UTP, the output switches to one saturation state (e.g., for an inverting Schmitt trigger).
• The output remains in this state until the input voltage drops below the LTP, at which point the output switches back to the opposite saturation state (e.g., ).

Importance of Hysteresis:

• Hysteresis Voltage: .
• Noise Immunity: In a basic comparator, noise near the reference voltage can cause the output to rapidly oscillate between states (chattering). Hysteresis prevents this by separating the switching points. Once the output switches at UTP, it will not switch back until the input drops significantly to the LTP, effectively ignoring small noise fluctuations.

Inverting Schmitt Trigger Derivation:
Consider an op-amp with the input signal applied to the inverting terminal (-). A voltage divider network consisting of resistors and connects the output to the non-inverting terminal (+), providing positive feedback.

The voltage at the non-inverting terminal is the threshold voltage, .

1. Upper Threshold Point (UTP):
Assume the output is at positive saturation, . The voltage at the non-inverting terminal is positive.

When exceeds , the output switches to .

2. Lower Threshold Point (LTP):
Now the output is at negative saturation, . The voltage at the non-inverting terminal becomes negative.

When drops below , the output switches back to .

Hysteresis Voltage ():

Voltage Limiters:
A voltage limiter (or clipper) is a circuit that restricts the output voltage of a waveform to a predetermined level, preventing it from exceeding a specific positive or negative value. It is used to protect sensitive circuits from excessive voltage or to shape waveforms.

Op-Amp Voltage Limiter Operation:
A basic op-amp limiter can be constructed using an inverting amplifier configuration with Zener diodes in the feedback loop.

• Circuit: Connect two Zener diodes back-to-back (series opposing) across the feedback resistor () of an op-amp.
• Positive Half Cycle: When the input is positive, the output tries to go negative. One Zener diode becomes forward-biased (acting like a normal diode with a drop of ~), and the other operates in the Zener breakdown region (at ). The output voltage is limited to .
• Negative Half Cycle: When the input is negative, the output tries to go positive. The roles of the Zener diodes reverse. The output voltage is limited to .
• This creates a symmetrically clipped waveform. Asymmetrical clipping can be achieved by using different Zener voltages or a single Zener diode.

Voltage to Frequency (V/F) Converter:
A V/F converter is a circuit whose output frequency is directly proportional to its input DC voltage. It effectively acts as an analog-to-digital converter by transmitting analog information as a pulse train frequency.

Principle of Operation:

1. Integration: The core of a V/F converter is typically an op-amp integrator. The input DC voltage () is integrated over time, producing a ramping output voltage. The slope of this ramp is proportional to the input voltage ().
2. Comparison: The integrator's output is fed to a comparator. When the ramp voltage reaches a predetermined reference threshold, the comparator changes state.
3. Reset and Pulse Generation: The comparator output triggers a one-shot (monostable multivibrator) or a discharge switch that rapidly resets the integrator capacitor to zero. This also outputs a distinct pulse.
4. Cycle Repeats: After the reset, the integration begins again.

Result: Higher input voltages cause the integrator to reach the threshold faster, resulting in more frequent resets and a higher output frequency. Thus, .

Frequency to Voltage (F/V) Converter:
An F/V converter performs the reverse operation of a V/F converter. It produces a DC output voltage that is directly proportional to the frequency of the input signal (e.g., a pulse train).

Principle of Operation:

1. Signal Conditioning: The input signal is first passed through a comparator or zero-crossing detector to ensure it is a clean pulse train of constant amplitude, regardless of the input waveform shape.
2. Monostable Multivibrator: Each rising (or falling) edge of the input pulse triggers a monostable multivibrator (one-shot). The one-shot generates a pulse of fixed width () and constant amplitude () for every input cycle.
3. Averaging/Low-Pass Filtering: The output of the one-shot is a train of pulses where the duty cycle depends on the input frequency. This pulse train is fed into an active low-pass filter (integrator).
4. DC Output: The low-pass filter averages these pulses. Since the pulses have constant width and amplitude, the average DC voltage is directly proportional to how frequently the pulses occur.

Equation: , where is the input frequency.

Successive Approximation ADC:
A Successive Approximation Register (SAR) ADC is widely used for its balance of high speed and high resolution. It uses a binary search algorithm to determine the digital equivalent of an analog input.

Block Diagram Components:

1. Sample and Hold (S/H) Circuit.
2. Comparator.
3. Successive Approximation Register (SAR).
4. Digital-to-Analog Converter (DAC).

Working Principle:

1. Initialization: The SAR sets the Most Significant Bit (MSB) to 1 and all other bits to 0 (e.g., 1000 for 4-bit).
2. DAC Conversion: This digital value is converted back to an analog reference voltage () by the internal DAC.
3. Comparison: The comparator compares the input analog voltage () with .
   • If , the MSB is kept at 1.
   • If , the MSB is reset to 0.
4. Successive Steps: The SAR moves to the next significant bit, sets it to 1, and repeats the DAC conversion and comparison process.
5. Completion: This process continues bit by bit down to the Least Significant Bit (LSB). After clock cycles (for an -bit ADC), the conversion is complete, and the SAR contains the final digital equivalent of the analog input.

Flash Type ADC (Parallel ADC):
The Flash ADC is a direct conversion technique that compares the analog input signal with multiple reference voltages simultaneously.

Architecture (for N-bit resolution):

1. Resistor Ladder: A precision resistor divider network consisting of resistors divides the reference voltage into distinct voltage levels.
2. Comparators: It requires comparators. One input of each comparator is connected to a specific node on the resistor ladder, and the other input is connected to the common analog input voltage ().
3. Priority Encoder: The outputs of all comparators are fed into a priority encoder circuit, which converts the "thermometer code" generated by the comparators into a binary output.

Operation:
As increases, it exceeds the reference voltages of the lower comparators one by one. All comparators with reference voltages below output a '1', and those above output a '0'. The encoder immediately translates this into the digital word.

Why it is the fastest:
The conversion happens in a single clock cycle. All comparisons are performed simultaneously (in parallel), avoiding the step-by-step sequential delays found in SAR or integrating ADCs. The only delay is the propagation delay of the comparators and the logic encoder.

R-2R Ladder DAC:
The R-2R ladder DAC uses a repeating network of only two resistor values: and . This overcomes the precision limitations of the weighted resistor DAC.

Working Principle:

• The circuit consists of a ladder network where series resistors are of value and shunt resistors are of value .
• The digital input bits () control electronic switches.
• Depending on whether a bit is '1' or '0', the respective switch connects the resistor either to the reference voltage () or to ground.
• Looking backward from any node in the ladder towards the LSB, the equivalent resistance is always . This creates a binary division of currents at each node.
• The current flowing into the virtual ground of an op-amp at the end of the ladder is proportional to the binary value of the digital input. The op-amp converts this current to an output voltage.

Advantages over Weighted Resistor DAC:

1. Fewer Resistor Values: It only requires two resistor values ( and ), making it much easier to manufacture accurately, especially in ICs.
2. Better Matching: Matching two resistance values is simpler than matching a wide range of values (like ).
3. Scalability: Easily expandable to higher bit resolutions without requiring extremely high resistance values.

Binary Weighted Resistor DAC:
A Binary Weighted Resistor DAC utilizes a summing op-amp amplifier configuration where the input resistors are scaled in a binary fashion.

Working Principle:

• For an -bit DAC, it has input resistors.
• The MSB is connected to a resistor of value .
• The next bit is connected to , the next to , and so on, up to the LSB which is connected to .
• Digital bits ($1$ or $0$) control switches that connect the resistors either to a reference voltage () or ground.
• The total current flowing into the summing junction of the op-amp is the sum of the currents from the active branches.
• .

Major Drawbacks:

1. Wide Range of Resistor Values: For high resolutions (e.g., 12-bit), the ratio between the LSB resistor and MSB resistor is massive (). If , the LSB resistor must be .
2. Difficulty in Manufacturing: It is very difficult and expensive to fabricate resistors with such varying values on a single IC while maintaining high precision and identical temperature coefficients.
3. Accuracy: Slight tolerances in the large-value resistors significantly impact the accuracy of the lower-order bits.

Sample and Hold (S/H) Circuit:
The function of an S/H circuit is to sample an continuously varying analog input signal at a specific instant and hold its voltage level constant for a specified period, usually until an ADC can process it.

Basic Circuit Diagram:
The basic circuit consists of an analog switch (often a MOSFET), a holding capacitor (), and two voltage buffers (op-amps with unity gain).
[Buffer 1] -> [Analog Switch] -> [Node tied to Capacitor ] -> [Buffer 2] -> Output.

Operation:

1. Sample Mode: A command pulse (Control voltage) turns the analog switch ON. The capacitor charges (or discharges) rapidly to the voltage level of the input signal through the low impedance of Buffer 1. The output follows the input.
2. Hold Mode: The control voltage turns the switch OFF. The capacitor is now isolated. Since Buffer 2 has an extremely high input impedance, the capacitor cannot discharge quickly. It "holds" the sampled voltage level constant at the output.

Key Parameters:

• Acquisition Time: Time required for the capacitor to charge to the input voltage during the sample phase.
• Droop Rate: The slow rate at which the held voltage decreases during the hold phase due to leakage currents.

Internal Block Diagram of 555 Timer:
The 555 Timer is a highly stable device for generating accurate time delays or oscillation.

Key Internal Components:

1. Voltage Divider: Three resistors connected in series between and Ground. They provide two reference voltages: and .
2. Comparators:
   • Upper Comparator (Threshold): Compares the 'Threshold' pin (Pin 6) input with the reference. If Pin 6 > , it outputs HIGH.
   • Lower Comparator (Trigger): Compares the 'Trigger' pin (Pin 2) input with the reference. If Pin 2 < , it outputs HIGH.
3. SR Flip-Flop: The outputs of the comparators are connected to the Set (S) and Reset (R) inputs of a flip-flop.
   • Lower comparator sets the flip-flop ().
   • Upper comparator resets the flip-flop ().
4. Discharge Transistor: An NPN transistor whose base is driven by the output of the flip-flop. When is HIGH, the transistor turns ON, providing a discharge path to ground for an external capacitor at Pin 7.
5. Output Stage: A high-current inverting buffer connected to the output, providing the final output at Pin 3.

Astable Multivibrator using 555 Timer:
In the astable mode, the 555 timer operates as a free-running oscillator, continuously toggling between high and low states without any external triggering.

Circuit Connections:

• Pins 2 (Trigger) and 6 (Threshold) are shorted together and connected to a timing capacitor () which charges through two resistors, and .
• Pin 7 (Discharge) is connected between and .

Operation:

1. Charging: The capacitor charges towards through and . When the voltage across reaches , the Upper Comparator triggers, resetting the internal flip-flop. The output goes LOW, and the discharge transistor turns ON.
2. Discharging: The capacitor now discharges through and the discharge transistor to ground. When the voltage drops to , the Lower Comparator triggers, setting the flip-flop. The output goes HIGH, the discharge transistor turns OFF, and the charging cycle repeats.

Timing Formulas:

• Time High ():
• Time Low ():
• Total Time Period ():
• Frequency ():

Monostable Multivibrator using 555 Timer:
In monostable (one-shot) mode, the 555 timer outputs a single pulse of a defined duration when triggered by a negative-going input pulse.

Circuit Connections:

• A timing resistor () is connected between and Pin 6/7.
• A timing capacitor () is connected between Pin 6/7 and ground.
• Pin 2 (Trigger) receives the external trigger pulse.

Operation:

1. Stable State: Initially, the flip-flop is reset, the output is LOW, and the discharge transistor is ON, keeping the capacitor shorted to ground (voltage is 0).
2. Triggering: A negative pulse is applied to Pin 2, dropping below . The Lower Comparator sets the flip-flop. The output goes HIGH, and the discharge transistor turns OFF.
3. Timing State: Capacitor begins charging towards through resistor .
4. Reset: When the capacitor voltage reaches , the Upper Comparator resets the flip-flop. The output goes LOW, the discharge transistor turns ON, rapidly discharging the capacitor back to 0V. The circuit returns to its stable state until the next trigger.

Pulse Width Calculation:
The duration of the high output pulse () is the time taken for the capacitor to charge from 0 to .

Phase Locked Loop (PLL):
A PLL is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase (and hence frequency) of an input reference signal.

Basic Building Blocks:

1. Phase Detector (PD) / Comparator: Compares the phase of the incoming reference signal () with the phase of the feedback signal from the VCO (). It generates an error voltage proportional to the phase difference between the two signals.
2. Low Pass Filter (LPF): The output of the phase detector contains high-frequency noise and AC components. The LPF filters these out to produce a smooth DC control voltage (). It also largely dictates the dynamic characteristics of the PLL, such as lock range and capture range.
3. Voltage Controlled Oscillator (VCO): An oscillator whose output frequency is directly proportional to the applied DC control voltage ().

Operation Loop:
If and are different, the PD generates a varying error voltage. The LPF converts this to a DC level, which pushes the VCO frequency towards . Once , the PLL is "locked," and a constant phase difference is maintained to hold the error voltage steady.

PLL Terminology:

1. Lock Range (Tracking Range):
   This is the range of frequencies over which the PLL can maintain synchronization (stay locked) with the incoming signal once lock has already been established. The lock range is usually centered around the VCO's free-running frequency. It is typically wider than the capture range.

2. Capture Range (Acquisition Range):
   This is the range of input frequencies over which an initially unlocked PLL can acquire lock with an incoming signal. If the input frequency is outside this range, the PLL will not be able to lock onto it. The capture range is determined primarily by the bandwidth of the Low Pass Filter (LPF).

3. Pull-in Time:
   This is the total time required by the PLL to acquire lock once an input signal (within the capture range) is applied. It is the transient time taken for the VCO frequency to shift from its free-running state and settle exactly onto the input frequency. It depends on the initial frequency difference and the characteristics of the LPF.

Key Parameters from a 555 Timer Datasheet:
When designing with a 555 timer, the datasheet provides critical limits and typical values:

1. Supply Voltage (): The safe operating voltage range, typically to (up to absolute maximum for standard bipolar 555).
2. Supply Current (): Quiescent current drawn by the IC, typically around to at , important for battery-powered circuits. CMOS versions (e.g., 7555) have much lower current.
3. Output Source/Sink Current: The maximum current the output pin (Pin 3) can drive. Standard 555 can typically sink or source up to .
4. Threshold/Trigger Voltage Levels: Confirms the internal voltage divider ratios, nominally for threshold and for trigger.
5. Maximum Operating Frequency: The highest reliable frequency in astable mode, usually specified around to for standard 555, up to for CMOS.
6. Timing Error/Accuracy: Initial accuracy of the timing equation (e.g., typical error) and temperature drift (e.g., ).

Comparison: Basic Comparator vs. Schmitt Trigger

1. Feedback Configuration:

   • Basic Comparator: Operates in an open-loop configuration (no feedback).
   • Schmitt Trigger: Operates using positive feedback.

2. Threshold Levels:

   • Basic Comparator: Has a single reference/threshold voltage ().
   • Schmitt Trigger: Has two distinct threshold voltages (Upper Threshold Point - UTP, and Lower Threshold Point - LTP).

3. Hysteresis:

   • Basic Comparator: No hysteresis (). Output can chatter if the input signal has noise near the threshold.
   • Schmitt Trigger: Exhibits hysteresis (). This provides built-in noise immunity.

4. Transition:

   • Basic Comparator: Output transitions are dependent on the speed of the input signal crossing the threshold. Slowly varying inputs cause slow output transitions.
   • Schmitt Trigger: Positive feedback ensures a very rapid, regenerative snap-action transition regardless of the input signal speed.

5. Application:

   • Basic Comparator: Used for precise level detection where noise is minimal (e.g., ZCD).
   • Schmitt Trigger: Used for squaring noisy or slowly varying signals, debouncing switches, and in oscillator circuits.

Applications of Phase Locked Loop (PLL):

1. FM Demodulation
2. Frequency Synthesizer
3. Frequency Multiplier/Divider
4. FSK (Frequency Shift Keying) Demodulator
5. Motor Speed Control

Detailed Explanation of Two Applications:

1. FM Demodulator:
When an FM signal is applied to the input of a PLL, the VCO tracks the instantaneous frequency of the input. Because the VCO frequency is controlled by the error voltage (output of the Low Pass Filter), this error voltage must vary identically with the modulating signal that originally varied the FM frequency. Therefore, the filtered control voltage () is the demodulated audio/data signal.

2. Frequency Synthesizer:
A PLL can generate multiple precise output frequencies from a single stable reference frequency (like a quartz crystal oscillator). By placing a digital divide-by-N counter in the feedback loop between the VCO and the Phase Detector, the PLL will lock when the divided VCO frequency equals the reference frequency (). Consequently, the output frequency is . By changing the integer , various precise output frequencies can be synthesized.