Unit 6 - Practice Quiz

1 What is the primary function of a comparator circuit?

2 In a basic operational amplifier comparator, what is typically the feedback configuration?

3 A zero crossing detector is a special case of a comparator where the reference voltage is set to:

4 What type of feedback is used in a Schmitt trigger circuit?

5 The difference between the upper threshold voltage and the lower threshold voltage in a Schmitt trigger is called:

6 What is the purpose of a voltage limiter circuit?

7 Which component is most commonly used along with an op-amp to design a voltage limiter?

8 What does a V/F converter do?

9 Which circuit produces a DC output voltage proportional to the frequency of its input signal?

10 An ADC (Analog to Digital Converter) is used to:

11 Which of the following is a common type of Digital to Analog Converter (DAC)?

12 What are the two primary modes of operation for a sample and hold circuit?

13 Which component in a sample and hold circuit is primarily responsible for storing the analog voltage during the hold phase?

14 How many pins does a standard 555 timer IC have?

15 Which mode of the 555 timer generates a continuous square wave (free-running)?

16 In the 555 timer monostable mode, what triggers the output pulse?

17 Which of the following is a key component of a Phase Locked Loop (PLL)?

18 What is the primary function of a Phase Locked Loop (PLL)?

19 According to a standard 555 timer datasheet, what is the typical purpose of Pin 3?

20 In a 555 timer, the internal voltage divider consists of three identical resistors. What is the typical value of each resistor?

21 In an op-amp basic comparator circuit without feedback, what happens when the non-inverting input voltage () slightly exceeds the inverting input voltage ()?

22 A zero crossing detector is essentially a comparator with the reference voltage set to what value?

23 In a Schmitt trigger, the difference between the upper threshold voltage () and the lower threshold voltage () is known as:

24 An inverting Schmitt trigger uses an op-amp with V and V. If the feedback resistors are and (where is connected to ground and connects output to non-inverting input), what is the upper threshold voltage ()?

25 What is the primary function of a Zener diode in an op-amp voltage limiter circuit?

26 A Voltage to Frequency (V/F) converter produces an output pulse train where which parameter is proportional to the input analog voltage?

27 Which of the following Analog-to-Digital converters (ADC) is known for the fastest conversion time?

28 In an ladder Digital-to-Analog Converter (DAC), what is the primary advantage over a weighted-resistor DAC?

29 In a Sample and Hold (S/H) circuit, what component is primarily responsible for holding the sampled voltage?

30 To minimize droop rate in a Sample and Hold circuit, the op-amp used as a voltage follower after the holding capacitor must have:

31 In a 555 timer configured in astable mode, the duty cycle is always greater than what percentage if simple external resistors and are used without a bypass diode?

32 A 555 timer is used as a monostable multivibrator with and . What is the approximate duration of the output pulse?

33 What is the function of the internal discharge transistor (pin 7) in a 555 timer?

34 Which three basic blocks constitute a Phase Locked Loop (PLL)?

35 In a PLL, what is the 'capture range'?

36 What role does the low pass filter play in the feedback loop of a PLL?

37 According to a standard 555 timer datasheet, what is the typical voltage range for proper operation ()?

38 On the 555 timer, pin 5 is the Control Voltage pin. What is its typical internal voltage level when no external connection is made, assuming a supply voltage of ?

39 A practical comparator differs from an ideal comparator primarily due to which of the following limitations?

40 If a 4-bit DAC has a full-scale analog output of $15$ V, what is its resolution (the step size)?

41 In an op-amp based inverting Schmitt trigger, the feedback fraction is . If the op-amp saturates at and a sinusoidal input is applied, what is the duty cycle of the output square wave?

42 In a Phase-Locked Loop (PLL) circuit, if the lock range is and the capture range is , which of the following relationships is generally true and why?

43 A 555 timer is configured in astable mode with , , and . If a control voltage of is applied to pin 5 (Control Voltage), what is the new upper threshold voltage and how does it affect the frequency compared to the standard operation?

44 An 8-bit successive approximation ADC operates with a clock frequency of . What is the maximum frequency of an input sinusoidal signal that can be digitized without aliasing if a sample-and-hold circuit is NOT used? (Assume full-scale peak-to-peak input).

45 In a charge-pump frequency-to-voltage converter, what is the primary purpose of the output low-pass filter's time constant, and what is the trade-off in increasing its value?

46 In a sample and hold (S/H) circuit, the 'droop rate' is primarily determined by which of the following parameters?

47 According to the standard NE555 datasheet, the 'Discharge' pin (Pin 7) is internally connected to which component?

48 An op-amp precision voltage limiter (clipper) uses a Zener diode in the feedback loop. Due to the op-amp's finite slew rate and gain-bandwidth product, what non-ideal behavior is most prominent at high input signal frequencies?

49 A basic open-loop op-amp comparator is used to detect when a slow-moving analog signal crosses . The signal has high-frequency Gaussian noise. To guarantee a single clean transition at the output without multiple rapid switchings, what modification is strictly necessary?

50 In a practical zero-crossing detector using a standard operational amplifier, what causes the output transition to be delayed with respect to the actual zero-crossing of the input signal?

51 An R-2R ladder DAC requires precise resistor matching. If the MSB resistor (2R) connected to the switch has a positive tolerance error, how does it predominantly affect the DAC's static characteristics?

52 In a PLL, an Exclusive-OR (XOR) gate is used as a phase detector. The input signal has a duty cycle. For the PLL to achieve lock with a zero steady-state error in frequency, what must the phase difference between the input and VCO signals be?

53 A 555 timer is used in monostable mode. If the trigger pin (Pin 2) is held low (below ) for a duration longer than the output pulse width , what happens to the output?

54 Design an inverting Schmitt trigger with and using an op-amp with saturation voltages of . Which circuit configuration and external reference voltage (applied to the non-inverting terminal through a resistor network) are required?

55 In a dual-slope integrating ADC, what is the primary advantage of making the integration time of the unknown input voltage exactly equal to an integer multiple of the local power line frequency period (e.g., )?

56 A bounded op-amp comparator uses back-to-back Zener diodes (with Zener voltage and forward drop ) in the feedback path. What is the fundamental difference in operation between placing this network in the feedback path versus placing it at the output of an open-loop comparator?

57 In a V/F converter operating on the charge-balance principle, the output frequency is proportional to the input voltage . If the reference current drifts by due to temperature variations, how is the output frequency affected?

58 During the 'hold' to 'sample' transition in a sample-and-hold circuit, the phenomenon where a fraction of the digital control signal is transferred to the hold capacitor via parasitic capacitances of the switch is known as:

59 What is the primary operational consequence of using a fully compensated operational amplifier (like the 741) as a comparator instead of a dedicated comparator IC (like the LM311)?

60 In a frequency synthesizer using a PLL, a divide-by- counter is inserted between the VCO output and the phase detector. If the reference frequency is , the VCO output frequency is . If the loop filter is not redesigned when is increased significantly, what happens to the closed-loop stability?