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Unit 4 - Notes

ECE131

Unit 4: Fundamentals of semiconductor devices and digital circuits

1. Digital Abstraction

The digital abstraction allows engineers to ignore the complex physics of analog semiconductor devices by treating signals as discrete values (0 and 1).

Voltage Levels and Logic States

In a digital system, information is represented by voltage levels.

  • Logic 0 (LOW): Represents 'False'. Usually associated with Ground (0V).
  • Logic 1 (HIGH): Represents 'True'. Usually associated with the Supply Voltage ( or , e.g., 5V or 3.3V).

However, real-world signals are not perfect 0V or 5V. Therefore, ranges of voltages are defined:

  • (Input Low Voltage): The maximum voltage that the input of a logic gate will recognize as a Logic 0.
  • (Input High Voltage): The minimum voltage that the input of a logic gate will recognize as a Logic 1.
  • (Output Low Voltage): The maximum voltage an output will produce when driving a Logic 0.
  • (Output High Voltage): The minimum voltage an output will produce when driving a Logic 1.

The Static Discipline

The Static Discipline is a contract between the sender (output of a gate) and the receiver (input of the next gate). It guarantees robust digital operation.

The Rule:
A digital system follows the static discipline if, given valid inputs (voltages within logic thresholds), it generates valid outputs.

  1. If Input , then Output must be (for a buffer) or (for an inverter).
  2. If Input , then Output must be (for a buffer) or (for an inverter).
  3. Forbidden Zone: The voltage range between and is undefined. Signals must transition through this region quickly and never stay there.

2. Boolean Logic and Combinational Gates

Boolean logic deals with variables that take on two discrete values. Combinational logic circuits have outputs that depend solely on the current state of the inputs (no memory).

Basic Logic Gates

1. NOT Gate (Inverter)

  • Operation: Inverts the input.
  • Boolean Expression:
Input (A) Output (Y)
0 1
1 0

2. AND Gate

  • Operation: Output is HIGH only if all inputs are HIGH.
  • Boolean Expression:
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

3. OR Gate

  • Operation: Output is HIGH if at least one input is HIGH.
  • Boolean Expression:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

4. Universal Gates (NAND / NOR)

  • NAND (Not AND): Output is LOW only if all inputs are HIGH. ()
  • NOR (Not OR): Output is HIGH only if all inputs are LOW. ()
  • Significance: Any Boolean function can be implemented using only NAND gates or only NOR gates.

5. Exclusive Gates (XOR / XNOR)

  • XOR (Exclusive OR): Output is HIGH if inputs are different. ()
  • XNOR: Output is HIGH if inputs are the same. ()

3. Electrical Characteristics of Gates

Fan-in and Fan-out

These parameters define the connection limits of logic gates.

Fan-in

  • Definition: The number of inputs a logic gate is designed to handle.
  • Physical Limitation: As fan-in increases, the internal capacitance increases, which increases the propagation delay (makes the gate slower). In CMOS technology, high fan-in gates (e.g., 4-input NAND) are often avoided by cascading smaller gates due to resistance accumulation.

Fan-out

  • Definition: The maximum number of standard logic inputs (load gates) that the output of a single logic gate can drive reliably.
  • Constraints:
    • DC Constraint (Current): The driving gate must be able to source or sink enough current to switch all attached load gates. If exceeded, voltage levels () may degrade into the forbidden zone.
    • AC Constraint (Timing): Each load adds capacitance. High fan-out increases the rise/fall times of the signal, potentially violating timing constraints.

Noise Margin

Noise margin is a measure of a digital circuit's immunity to noise (electromagnetic interference). It represents the amount of noise voltage that can be superimposed on a signal without causing a logic error.

There are two noise margins:

  1. Noise Margin High ():

    • This ensures that even if the Logic 1 output drops slightly due to noise, it is still recognized as a Logic 1 by the receiver.

  2. Noise Margin Low ():

    • This ensures that even if the Logic 0 output rises slightly due to noise, it is still recognized as a Logic 0 by the receiver.

Analysis:

  • and must be positive numbers.
  • The larger the noise margin, the more robust the circuit is against interference.

4. PN Junction and Zener Diode

PN Junction Diode

Formed by joining P-type semiconductor (rich in holes) and N-type semiconductor (rich in electrons).

Characteristics

  1. Unbiased: A depletion region forms at the junction, creating a potential barrier (approx. 0.7V for Silicon, 0.3V for Germanium).
  2. Forward Bias (Anode +, Cathode -):
    • External field opposes the internal barrier.
    • Once voltage exceeds the Knee Voltage (), the depletion region narrows, and heavy current flows (Diffusion current).
    • Acts as a closed switch (on).
  3. Reverse Bias (Anode -, Cathode +):
    • External field aids the internal barrier.
    • Depletion region widens.
    • Only a tiny Reverse Saturation Current () flows (due to minority carriers).
    • Acts as an open switch (off).

Analysis Models

  • Ideal Model: Short circuit when forward biased (); Open circuit when reverse biased.
  • Constant Voltage Drop Model (Practical): When ON, replaced by a voltage source of 0.7V (Si).

Zener Diode

A heavily doped PN junction diode designed to operate in the reverse breakdown region.

Characteristics

  • Forward Bias: Acts like a normal diode.
  • Reverse Bias:
    • Initially conducts negligible current.
    • At a specific voltage called Zener Voltage (), the current increases sharply while the voltage remains constant.
  • Mechanisms:
    • Zener Effect (): Electric field rips electrons from covalent bonds.
    • Avalanche Effect (): Accelerated carriers collide with atoms, dislodging more carriers (chain reaction).

Applications

  1. Voltage Regulator: Maintains a constant voltage across a load despite variations in input voltage or load current.
  2. Reference Element: Provides precise reference voltages in circuits.
  3. Protection: Used to clamp voltage spikes.

Testing of Diodes

Using a Digital Multimeter (DMM) in "Diode Test" mode:

  • Good Diode:
    • Forward Bias: Reads approx 0.5V to 0.7V.
    • Reverse Bias: Reads "OL" (Over Limit/Open).
  • Short Diode: Reads ~0V in both directions (beep sound).
  • Open Diode: Reads "OL" in both directions.

Diode Applications (General)

  • Rectifiers: Converting AC to pulsating DC (Half-wave and Full-wave Bridge).
  • Clippers: Removing parts of a signal waveform (limiting voltage).
  • Clampers: Shifting the DC level of a signal.

5. Bipolar Junction Transistor (BJT)

A three-terminal current-controlled device. The terminals are Emitter (E), Base (B), and Collector (C).

Structure and Types

  • NPN: A P-type layer sandwiched between two N-type layers. (Current flows C to E).
  • PNP: An N-type layer sandwiched between two P-type layers. (Current flows E to C).
  • Doping Profile: Emitter is heavily doped, Base is lightly doped and very thin, Collector is moderately doped and physically large (for heat dissipation).

Basic Operation (NPN Focus)

Current flow is controlled by the Base-Emitter current ().


(where is the current gain, typically 50-300).

Operating Regions

  1. Cutoff: BE junction Reverse Biased, BC junction Reverse Biased. . Switch is OFF.
  2. Active Region: BE junction Forward Biased, BC junction Reverse Biased. Used for Amplification. Output is linear amplification of input.
  3. Saturation: BE junction Forward Biased, BC junction Forward Biased. is maxed out. Switch is ON (Closed). .

Testing of BJT

A BJT can be modeled as two back-to-back diodes for testing purposes.

  • NPN Test:
    • Base(+) to Emitter(-): 0.7V drop.
    • Base(+) to Collector(-): 0.7V drop.
    • Collector to Emitter: OL (Open).
  • Any other combination: OL.
  • If continuity (0V) is found between C and E, the transistor is shorted.

6. MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)

A voltage-controlled device. It has very high input impedance because the Gate is insulated from the channel by silicon dioxide ().

Representation and Structure

Terminals: Gate (G), Drain (D), Source (S), Body (B).

  • N-Channel (NMOS): Conduction via electrons. Positive voltage at Gate attracts electrons to form a channel.
  • P-Channel (PMOS): Conduction via holes. Negative voltage at Gate attracts holes.

Circuit Symbols:

  • Enhancement Mode: Broken line between Source and Drain (normally off).
  • Depletion Mode: Solid line between Source and Drain (normally on).
  • arrow on Source indicates direction of conventional current (Out for NMOS, In for PMOS).

Characteristics (Enhancement NMOS)

  1. Transfer Characteristics ( vs ):

    • Threshold Voltage (): Minimum Gate-Source voltage required to create the inversion layer (channel).
    • If , (Cutoff).
    • If , current flows.

  2. Output Characteristics ( vs ):

    • Cutoff Region: Switch OFF.
    • Ohmic / Linear / Triode Region: ( is small). The MOSFET acts as a voltage-controlled resistor. increases linearly with .
    • Saturation Region: (). The channel "pinches off" at the drain end. Current becomes constant regardless of . Used for amplification.

Note: In Digital Logic (CMOS), MOSFETs switch between Cutoff (OFF) and Triode (ON), skipping saturation mostly.

7. Handling of Integrated Circuits - ESD Phenomena

Electrostatic Discharge (ESD)

ESD is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown.

ESD Mechanism in Semiconductors

  • Gate Oxide Breakdown: MOSFETs (and CMOS ICs) have a very thin oxide layer at the Gate. Static electricity (which can reach thousands of volts, e.g., walking on carpet can generate >10,000V) can easily puncture this layer.
  • Effect: A puncture causes a short circuit between the Gate and Channel, permanently destroying the device.
  • Latent Defects: Sometimes ESD weakens the device without killing it immediately, leading to failure later in operation (unreliable).

Protection and Handling Rules

  1. Antistatic Wrist Straps: Engineers must wear grounded wrist straps to drain charge from their body before touching ICs.
  2. Antistatic Mats: Workbenches should have conductive mats connected to the ground.
  3. ESD Safe Packaging: ICs are stored in antistatic bags (silver/grey shielding bags) or conductive foam.
  4. Humidity Control: Dry air promotes static buildup; maintaining humidity helps dissipate charge.
  5. Handling Technique: Hold PCBs by the edges; avoid touching the pins/leads of the ICs directly.